FPGA Implementation lead

About Us

At Ludwig Computing, we are solving the energy efficiency problem of intelligent compute. Our novel co-designed approach is optimized to deliver radical improvements in energy efficiency and performance across a wide range of compute-intensive workloads. We are building a future where high-performance computing is powered by leaner, smarter, and extremely efficient hardware and software platforms. Join us at the ground floor as we build the future of intelligent compute.

About the Role

We are hiring an experienced FPGA / RTL implementation lead to help drive the development of Ludwig’s first hardware acceleration platform.

We are looking for a technically exceptional and highly practical engineer who can translate a broader hardware architecture into a staged FPGA implementation plan: concrete module boundaries, interfaces, validation milestones, bring-up steps, and realistic development timelines. The ideal candidate is comfortable moving between system-level architecture, RTL design review, FPGA bring-up planning, performance analysis, and day-to-day technical mentorship of junior engineers.

You will work directly with the founding team to make the FPGA implementation path more deterministic: defining what needs to be built, sequencing the work, assigning well-scoped technical tasks, reviewing progress, and helping the team converge toward a working prototype. This role requires someone who can provide strong technical direction while still being close enough to the RTL to review designs, debug critical issues, and contribute directly to high-risk or blocking pieces when needed. A central part of the role is breaking down complex hardware goals into implementable blocks, identifying risks early, guiding verification strategy, and helping the team make steady progress toward working hardware.

This is a senior technical leadership role at the intersection of FPGA systems, RTL design, hardware acceleration, and hardware-software co-design. Engineers excited by early-stage environments, high-performance compute, and turning ambitious hardware architectures into executable engineering plans and measured FPGA results are encouraged to apply.

Responsibilities

• Lead the FPGA implementation plan for Ludwig’s first hardware acceleration prototype, from architecture decomposition through block-level validation and system bring-up.

• Translate high-level hardware architecture into concrete module boundaries, interfaces, test plans, ownership assignments, and development milestones.

• Build and maintain realistic engineering roadmaps, including task sequencing, implementation estimates, integration dependencies, and risk-based schedule adjustments.

• Review and guide RTL development across datapaths, control logic, memory interfaces, and host/FPGA communication paths, contributing directly to critical or blocking pieces when needed.

• Guide FPGA bring-up and integration on modern FPGA platforms and development flows.

• Work closely with interns and junior engineers by turning roadmap items into well-scoped implementation tasks, reviewing designs and code, and helping unblock difficult RTL or FPGA issues.

• Establish strong verification practices, including golden-model comparison, deterministic unit tests, simulation infrastructure, integration tests, and clear definitions of done for each block.

• Analyze resource utilization, timing, memory bandwidth, and throughput bottlenecks, and use those analyses to guide architecture and implementation decisions.

• Collaborate with the broader team to align RTL and FPGA work with Ludwig’s hardware roadmap, software integration needs, and long-term platform direction.

Requirements

• Significant experience with FPGA and/or ASIC RTL development using Verilog or SystemVerilog, ideally including prior ownership of a nontrivial subsystem or prototype.

• Strong understanding of digital design, pipelined datapaths, finite-state machines, memory systems, clocking/reset, timing closure, and hardware verification.

• Experience bringing up nontrivial designs on FPGA platforms using Vivado or comparable FPGA toolchains.

• Familiarity with AXI, AXI-Lite, AXI-MM, DMA-based data movement, host/FPGA interfaces, and memory-mapped control.

• Ability to decompose complex hardware systems into clean module boundaries, interfaces, verification plans, and implementation milestones.

• Ability to estimate implementation complexity, identify critical-path risks, and turn uncertain hardware goals into executable engineering plans.

• Experience debugging RTL and FPGA issues across simulation, synthesis, place-and-route, timing reports, hardware bring-up, and host-side integration.

• Comfortable mentoring interns or junior engineers while setting clear technical direction, reviewing work in detail, and staying close enough to the implementation to provide specific, technically grounded guidance.

• Strong written and verbal communication, including the ability to write clear specs, design notes, test plans, and roadmap documents.

• Comfortable owning and driving ambiguous engineering projects in a fast-paced early-stage environment.

Bonus if You Have

• Experience with cloud FPGA deployment, FPGA development kits, accelerator shells, or remote FPGA bring-up flows.

• Experience with AMD/Xilinx UltraScale+ devices, Alveo cards, or comparable high-end FPGA platforms.

• Background in hardware acceleration, systolic arrays, matrix engines, low-precision arithmetic, or high-throughput dataflow architectures.

• Experience designing or integrating control processors, DMA engines, NoCs, or custom accelerator control planes.

• Familiarity with C/C++, Python, cocotb, Verilator, SystemVerilog testbenches, or hardware/software co-simulation.

• Experience with fixed-point arithmetic, low-precision datapaths, packed data formats, scaling, accumulation, or randomized hardware blocks.

• Prior experience leading small hardware teams, mentoring interns, or serving as the technical owner for an FPGA/ASIC prototype or accelerator project.

• Experience taking designs from early architecture through simulation, synthesis, timing closure, board/cloud bring-up, and measured performance.

What You’ll Gain

• A foundational role in turning Ludwig’s hardware acceleration architecture into a working FPGA prototype.

• The opportunity to work across architecture, RTL, FPGA bring-up, software integration, and long-term hardware planning.

• Technical ownership over real accelerator blocks, from architecture decomposition through measured FPGA results.

• The chance to mentor a small technical team and shape the engineering culture around rigorous, roadmap-driven hardware development.

• Deep collaboration with a founding team building next-generation compute through hardware-software co-design.