Do you want to tackle the biggest questions in finance with near infinite compute power at your fingertips?

G-Research is a leading quantitative research and technology firm, with offices in London and Dallas.

We are proud to employ some of the best people in their field and to nurture their talent in a dynamic, flexible and highly stimulating culture where world-beating ideas are cultivated and rewarded.

This is a hybrid role based in our new Dallas infrastructure hub where we work on the latest technologies in a cutting-edge environment.

The role

The Low Latency Engineering Group is responsible for a low-latency trading system that is a critical part of our clients’ global investment platform. The group includes teams responsible for market-data, order-entry and order-execution functions.

This team has deployed a bespoke, cutting-edge FPGA-based platform that enables our clients to exploit low-latency opportunities in the most competitive markets in the world. The team is now expanding to accelerate the deployment of this platform more widely.

The LLE FPGA team is a small team of software and hardware engineers. The team is responsible for its own QA, tooling and continuous delivery pipelines. We value flexibility and willingness to collaborate on the problems we work on alongside our clients.

Key responsibilities of the role include:

• Developing RTL HDL in SystemVerilog
• Writing automated test benches
• Writing scripts in Python
• Developing some software in C/C++
• Building Continuous Delivery pipelines for all components

Who are we looking for?

You will be an enthusiastic and capable Engineer who is able to solve real-world problems in HDL and software. You should be flexible and proactive, with the ability to make complex systems work and to debug them when they don’t. You should enjoy working as part of a collaborative engineering team.

The ideal candidate will have the following skills and experience:

• Practical experience of hardware/software co-design for FPGA-based systems
• HDL development skills in SystemVerilog
• Experience with Xilinx FPGA Build Process
• System analysis and debugging skills
• Ability to communicate well with technical and non-technical people
• Experience working in a collaborative engineering team, preferably using a git-based development workflow

The following skills and experiences are beneficial, but not essential:

• C or C++ knowledge
• Python knowledge

Why should you apply?

• Market-leading compensation plus annual discretionary bonus
• Lunch provided in the office (via GrubHub)
• Informal dress code and excellent work/life balance
• Excellent paid time off allowance of 25 days
• Sick days, military leave, and family and medical leave
• Generous 401(k) plan
• 16-weeks’ fully paid parental leave
• Medical and Prescription, Dental, and Vision insurance
• Life and Accidental Death & Dismemberment (AD&D) insurance
• Employee Assistance and Wellness programs
• Generous relocation allowance and support
• Great selection of office snacks, and hot and cold drinks
• Free on-site gym and car parking