FPGA Design Verification Engineer

Seeking a highly skilled FPGA Design Verification Engineer to ensure the functionality, reliability, and quality of FPGA-based designs within high-performance wireless systems.

In this role, you will lead verification efforts for FPGA IP and subsystems, collaborate cross-functionally with design and system teams, and contribute to the adoption of AI-assisted verification methodologies to enhance efficiency and coverage.

Key Responsibilities

Design Verification & Validation

• Lead and execute verification strategies for FPGA IP and subsystems in 4G/5G radio units
• Develop and maintain robust verification environments using SystemVerilog and UVM
• Create constrained-random test scenarios, assertions, and scoreboards
• Perform simulation, debugging, and analysis using industry-standard tools such as Synopsys VCS
• Analyze coverage metrics and drive closure of functional and code coverage gaps
• Conduct root-cause analysis of RTL and system-level issues independently

AI-Driven Verification

• Contribute to the development and implementation of AI-assisted design verification workflows
• Identify opportunities to leverage AI in test generation, stimulus creation, log analysis, and coverage optimization
• Evaluate and refine AI-based methodologies to improve verification productivity
• Document best practices and contribute to continuous improvement initiatives

Collaboration & System Integration

• Partner with FPGA design teams to review specifications, interfaces, and edge cases
• Participate in design reviews and architectural discussions
• Collaborate with system, radio, and software teams to ensure end-to-end validation
• Support system integration, regression testing, and overall verification processes

Automation & Infrastructure

• Develop and enhance automation frameworks for simulation, regression, and reporting
• Utilize scripting (e.g., Bash) to manage large-scale regression runs
• Continuously improve verification processes through tooling and workflow enhancements

Leadership & Strategic Impact

• Provide technical leadership on complex verification challenges and deliver innovative solutions
• Offer insights into industry trends to influence long-term product and organizational strategy
• Contribute to research, product planning, and cost optimization initiatives
• Act as a consultant on critical projects impacting business objectives
• Mentor team members and communicate progress effectively with senior leadership
• Drive standardization and contribute to the development of new product concepts

Required Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related discipline
• 3+ years of experience in FPGA or ASIC design verification
• Proven experience verifying FPGA designs in wireless or high-speed systems
• Strong expertise in SystemVerilog and simulation-based verification
• Hands-on experience with UVM methodology
• Solid understanding of RTL design principles and debugging techniques
• Experience with Synopsys VCS or similar simulation tools
• Proficiency with Git/GitHub and collaborative development workflows
• Experience in DV automation using scripting (e.g., Bash)
• Interest or exposure to AI/ML-driven verification approaches
• Knowledge of LTE, 5G NR, CPRI/eCPRI, PTP, or O-RAN architectures
• Familiarity with high-speed interfaces such as AXI, Ethernet, PCIe, JESD204B/C, and SERDES
• Experience with Python and TCL for verification automation
• Exposure to system-level verification or FPGA-in-the-loop environments