FPGA Design & Verification Engineer –

FPGA Design & Verification Engineer (UVM) (Hybrid Sunnyvale, CA)

We are looking for an FPGA Design & Verification Engineer (UVM) for a global aerospace company. In this role, you will design, verify, and integrate ASIC/FPGA solutions for high-speed digital and DSP applications using UVM-based verification methodologies, while supporting System-on-Chip (SoC) development, FPGA platforms, automation scripting, and cross-functional collaboration to deliver complex, high-performance systems.

This is a 7-month contract (extensions likely), 40-hour-per-week (5-day 8-hour shifts per week) role, this is a hybrid role in Sunnyvale, CA.

This is a W-2 role as a Stage 4 Solutions employee. Health benefits and 401K are offered.

Responsibilities

• The selected candidate will be responsible for ASIC & FPGA development on R&D program. This engineer with have experience in developing, testing, and integrating digital signal processing (DSP), high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms.
• Experience with COTS based control platforms and embedded processors on FPGA platforms. This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts.
• Cross discipline collaboration with Systems Architects, RF/Analog & Digital Circuit designers and ASIC/FPGA engineers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
• The selected candidate will also provide support and technical direction to junior engineers. Overall contribution to design, simulation, verification, integration & test of complex, high speed products.
  
  

Requirements

• Must be a U.S. citizen.
• Bachelor of Science or higher from an accredited college in Electrical Engineering or related discipline, or equivalent experience/combined education.
• 11+ years of experience as an FPGA Design/Verification engineer
• Strong experience with UVM
  
  

Please submit your resume to our network at http://www.stage4solutions.com/careers/(Please apply to the FPGA Design & Verification Engineer (UVM) (Hybrid Sunnyvale, CA) role.

Please feel free to forward this opportunity to others who may be interested.

Stage 4 Solutions is an equal-opportunity employer. We celebrate diversity and are committed to providing employees with an inclusive environment that is free of discrimination and harassment. All employment decisions are based on the job requirements and candidates qualifications, without regard to race, color, religion/belief, national origin, gender identity, age, disability, marital status, genetic information or other applicable legally protected characteristics.

Compensation: $100.00/hr - $125.00/hr