FPGA Design Engineer

Resquant 

📍 Warsaw, Poland 🇵🇱

full-time
mid-level
27000
hybrid
Posted —

Key Skills

FPGAVHDLVerilogPCIeASIC

Industry

SemiconductorConsumer Electronics

Job Description

Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture.


We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies.


Position: FPGA Design Engineer (multiple)


Compensation: 27,000–35,000 PLN gross/month

Employment type: Polish employment contract (Umowa o Pracę / UoP) only; B2B cooperation is not available.


Resquant is looking for highly skilled FPGA Digital Design Engineers for various positions. This is a great opportunity to join a rapidly growing startup at an early stage, working on the latest trends in chip security and cryptography.


Main responsibilities:

  • Developing and implementing RTL at the block and subsystem level for quantum-resistant cryptographic algorithms and cryptographic processors.
  • Defining micro-architecture, performing simulations, and synthesizing digital design.
  • Top-level architecture modeling and integration with 3rd party IP (e.g. RISC-V).
  • Tuning up countermeasures against side-channel attacks.
  • Preparing input for verification environment for FPGAs and ASICs.
  • Participation in certification and technical documentation development.
  • Cooperation with ASIC backend team.


Our requirements:

  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field
  • 5+ years (Mid-level) or 8+ years for Senior-level of hands-on experience in FPGA design and development.
  • Proficient in any VHDL/Verilog/SystemVerilog for RTL design.
  • Knowledge of the ASIC design process.
  • Experience with timing analysis, synthesis, and implementation workflows.
  • Experience with high-speed interfaces and protocols such as PCIe, Ethernet, AXI.
  • Knowledge of system integration, including embedded processors.
  • Ability to work independently or strong cooperation skills to work within a cross-functional team.
  • Strong problem-solving and analytical thinking skills.
  • EU citizenship.
  • Candidates must be eligible for employment under a Polish employment contract (UoP)


Preferred candidates with:

  • Knowledge in the field of cryptography.
  • Experience in side-channel attacks and countermeasures.
  • Experience with space technologies and requirements.
  • EU/NATO security clearance.


What do we offer:

  • Full-time Senior and Mid positions in a 3-year project
  • Salary range: 27,000–35,000 PLN gross/month depending on experience and seniority.
  • Employment exclusively under an employment contract (UoP). B2B cooperation is not available.
  • Participation in projects aimed at providing a backbone for chip security for dual-use markets.
  • Flexible working hours.
  • Ability to work remotely (Hybrid/Full).
  • Equity options.
  • Broad Technical Ownership.
  • Innovation and Cutting-Edge Projects.
  • Opportunity to attend closed events with military representatives.