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Digital IC Design Engineer_Taipei

📍 Taipei, Taiwan 🇹🇼

full-time

mid-level

Expired

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synthesistimingDFTQCdesign

SemiconductorConsumer Electronics

Job Description

Digital IC design BE flow/methodology improvement
Digital IC design BE task execution and management
a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion
b) STA timing analysis & fixing
c) Netlist level QC. e.g., CLP.
Design and clock structure optimization for PPA (Performance, Power, Area). Work closely with FE RTL designers and PD APR teams
Job grade will be offered according to the candidate’s experience and expertise

Requirement

MS degree of engineering or above
Over 2 years of SOC digital design experience, with primary responsibility in one or more of the following BE tasks:
a) Physical aware synthesis (1+ years)
b) STA timing analysis & fixing (1+ years)
c) Pre/Post-netlist QC. e.g., CLP (1+ years)
d) DFT-SCAN, DFT-MBIST insertion and pattern generation (1+ years)
Strong communication skill across teams
Experience in any of the following is a plus:
a) SOC clock/reset structure and design constraints
b) Lower power design & integration flows
c) APR physical design implementation flows
d) Floor Plan, Package design