Design Verification Engineer

Duties/Responsibilities:

· Develop verification testbench components for chip/module level using SystemVerilog.

· Use high-level concepts (Object-oriented, UVM, etc) to develop an extendable environment.

· Define and execute detailed verification plan from spec working with architects and designer engineers

· Incorporate code coverage, functional coverage, assertions, cover groups, etc to achieve 100% verification completeness before tape-out.

· Debug tests, and regression failures.

· Participate in silicon debugging and analysis.

Qualifications

· MS in Computer or Electrical Engineering with a minimum of 5+ years of experience in design/verification management of highly complex projects.

· Organized and creative thinker, motivated, and independent learner who can multitask in a dynamic environment, able to create and implement new solutions where required.

· Must be good in building verification environments preferably using the verification subset of high-level languages like System Verilog (UVM).

· Understanding or prior experience with Industry standard protocols like DDR4/DDR5 is preferred