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CPU Verification Engineer

📍 Bengaluru, India 🇮🇳

full-time

senior

Expired

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verificationCPythonVerilogassembly

SemiconductorConsumer Electronics

Job Description

Key Qualifications

Preferably BE/B.Tech/ME/M.Tech in EEE/ECE/CSE with 5-12 years of relevant industry experience.
Should have experience in verification methodology.
Architecting and development of testbench, test-bench components for ISA features, clock/reset/power features of processor.
Strong assembly and CPU (x86/ARM/RISC-V) architecture knowledge.
Strong in C, C++, Verilog, and scripting (Perl, Python) languages.
Ability to work independently and across geographies

Requirement

Role and Responsibilities

Work with CPU architects to get understand processor micro-architecture
Develop detailed test and coverage plans for ISA and micro-architecture features
Design and develop component, block and core level testbenches including stimulus engines, microarchitectural models, checkers
Build architectural tools for ISA level verification
Develop stimulus generators that scale from pre-silicon to emulation and post-silicon domain
Execute verification plans, including DV environment bring-up, regression enabling for all features under your care, debug of the test failures
Track and report DV progress using a variety of metrics, including bugs and coverage

Preferred Qualifications

Deep knowledge in processor verification function and architecture, in areas such as cache coherence, memory ordering and consistency, prefetching, branch prediction, renaming, speculative execution, and memory translation
Knowledge in Random Instruction Sequencing (RIS) and testing associated as block/unit and chip level for proving correctness
Have lead a small team of verification engineers doing CPU verification
Advanced techniques such as formal, assertions, and silicon bring up a plus
Experience in writing test plans, portable benches, transactors, and assembly
Experience with many different verification methodologies and tools such as simulators, coverage collection, gate level simulation
Able to develop test bench and work independently on a block/unit of the design