CPU Design Verification Engineer
MediaTek ↗
📍 Hsinchu, Taiwan 🇹🇼
full-time
junior
Expired
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Key Skills
VerilogSystemverilogOOPUVMDebugging
Industry
Semiconductor
Job Description
Job Description
- Study Design and define DV Plan for Mentor Review.
- Base on DV Plan coding Random-Stimulus, Checking Mechanism, Functional Coverage.
-
Run-Simulation then debug and identify fail reason, Fixing DV Environment Problem (Random/Check/Cover).
- 2 Years or Less design verification experience or who interesting with design verification.
- Familiar Verilog or Systemverilog is required.
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OOP or UVM is preferred.
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Key Skills
VerilogSystemverilogOOPUVMDebugging
Industry
Semiconductor