Analog Mixed-Signal IC Design Engineer

Key Responsibilities:

1. Circuit Architecture & Design.

• Design high-speed (>100MS/s) Successive Approximation Register (SAR) ADCs for applications like 5G, radar, and data converters.
• Optimize critical blocks: capacitor DAC arrays, high-speed comparators, bootstrapped switches, and digital control logic.
• Achieve target specifications: ENOB (Effective Number of Bits), SFDR (Spurious-Free Dynamic Range), power efficiency (FOM < 10 fJ/step).

2. Performance Optimization.

• Mitigate nonlinearity via capacitor matching techniques (common-centroid, dummy units).
• Reduce kickback noise, clock jitter, and metastability in comparators.
• Develop calibration algorithms (e.g., background LMS for capacitor mismatch).

3. Process & Technology Integration.

• Implement designs in advanced nodes (FinFET 7nm/5nm, 28nm CMOS).
• Model parasitics, device mismatch, and PVT (Process-Voltage-Temperature) variations.
• Collaborate with layout teams on matched routing, shielding, and EM/IR reliability.

4. Validation & Testing.

• Develop test plans for lab characterization (e.g., using high-speed oscilloscopes, BERTs).
• Perform post-silicon validation: INL/DNL, dynamic performance, jitter tolerance.
• Support ATE (Automated Test Equipment) program development for production.

5. Cross-Functional Collaboration.

• Work with systems team on ADC integration (e.g., in RF transceivers or SoCs).
• Document design specs, simulation reports, and silicon performance.

Required Qualifications:

1. With more than 8 years relevant experience in similar filed in semiconductor industry.

2. Technical Skills:

• Proficiency in EDA tools: Cadence Virtuoso, Spectre, HSPICE, MATLAB/Python for modeling.
• Deep understanding of ADC fundamentals: sampling theory, quantization noise, metastability.
• Experience with high-speed challenges: clock distribution, comparator offset cancellation, charge injection.
• Familiarity with mixed-signal verification (AMS, Verilog-A).

3. Preferred Expertise:

• Tape-out experience with SAR ADCs >500MS/s (e.g., 8–12 bits).
• Knowledge of hybrid architectures (e.g., SAR-assisted pipelined, time-interleaved SAR).
• Scripting for automation (Python, Tcl).