ASIC SOC RTL Design Architect

Hi All,

📢 We are Hiring: Senior RTL Design ( Micro-architecture ) Engineers.

Experience:

• 6-25+ Years.

📍 Locations:

• India: Bengaluru, Hyderabad, Pune & Ahmedabad.
• San Jose (Bay Area), USA
• Austin, USA
• Eligibility (USA): U.S. Permanent Residents (Green Card holders).

❖ Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics.

❖ Engineering 6+ years of ASIC SOC RTL ( Micro-architecture ) experience.

❖ ARM Processor Integration Preferably M55 is a Must.

❖ Strong understanding of design concepts.

❖ ASIC flow Understanding of SDC Understanding STA reports.

❖ Understanding of CDC logic Knowledge of lint rules and exceptions.

❖ Design and use of block level simulations to bring up IP.

❖ Knowledge of AMBA buses and when to use them.

❖ Knowledge on common processor architectures (ARM, RiscV).

❖ FPGA experience includes part selection, pin assignment, timing constraints, synthesis, and debug of design in the FPGA.

❖ Relevant tool experience such as: Socrates, Core Consultant in addition to standard simulation tools (xcellium, vcs, etc) JTAG debugging experience (Coresight, Lauterbach, etc).

❖ Low power design techniques / UPF As an RTL Engineer, Candidate will be responsible to work at IP, Subsystem, or SoC-related tasks.

Responsibilities:

❖ Collaborate with architects, pre- and post-silicon verification teams to meet deadlines.

❖ Coordinate with customer leads, ensuring all deliverables and timelines are met.

If this opportunity interests you—or if you know someone suitable—please send your updated resume to: 📧 [email protected].

Referrals are highly appreciated.

Best regards,

Maruthy Prasaad

Associate VLSI Manager - Talent Acquisition | Visakhapatnam

Eximietas Design

[email protected]

+91 8088969910.