ASIC RTL design Engineer
Cyient ↗
📍 Duisburg, Germany 🇩🇪
full-time
mid-level
remote
Expired
Posted —
This job posting has expired
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Key Skills
RTLSoCVerilogAMBAsynthesis
Industry
SemiconductorTelecommunications
Job Description
- Good knowledge on the digital concepts and ASIC flow
- Experience in RTL coding and micro-architect
- Must have hands on experience with SoC design and integration.
- Experience in Verilog/System-Verilog is a must.
- knowledge of AMBA protocols - AXI, AHB, APB
- Basic knowledge on verification
- Understanding of Memory controller designs and microprocessors is an added advantage
- Experience in Synthesis / Understanding of timing concepts is a plus.
- Excellent oral and written communications skills
- Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.
- Remote working and Travel occasionally to customer location(Eindhoven )
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Key Skills
RTLSoCVerilogAMBAsynthesis
Industry
SemiconductorTelecommunications
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