ASIC RTL Design Lead/Engineers

Digital Design Engineer (Senior & Mid-Level) | ASIC / SoC Development

Location: Bengaluru, India

Experience: 3+ Years / 10+ Years

Employment Type: Full-Time

About the Role

We are seeking highly motivated Digital Design Engineers to contribute to next-generation silicon development programs. In this role, you will work across architecture definition, RTL development, and implementation, enabling high-performance and power-efficient ASIC/SoC designs.

You will collaborate closely with architecture, verification, and physical design teams to deliver production-quality silicon from specification through tape-out.

Role 1: Senior Digital Design Engineer (10+ Years Experience)

Responsibilities

• Define and drive digital design architecture for complex SoC and ASIC subsystems
• Translate micro-architecture specifications into scalable and high-quality RTL implementations
• Refine functional requirements throughout the design lifecycle in collaboration with cross-functional teams
• Implement low-power design methodologies aligned with system-level goals
• Perform synthesis, timing closure, and design optimization
• Drive design quality through CDC analysis, constraint development, and sign-off readiness
• Partner with verification and physical design teams to ensure successful integration and tape-out

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or related discipline
• 10+ years of experience in digital ASIC/SoC design
• Strong expertise in RTL design using SystemVerilog/Verilog
• Hands-on experience in ASIC synthesis, timing analysis, and CDC methodologies
• Working knowledge of P&R flows and low-power design using UPF
• Deep understanding of end-to-end digital design and implementation flow

Preferred Qualifications

• Experience owning complex IP or subsystem delivery
• Exposure to advanced node designs and power optimization techniques
• Strong debugging and design closure experience across multiple tape-outs

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Role 2: Digital Design Engineer (3+ Years Experience)

Responsibilities

• Define and implement digital design blocks based on architecture specifications
• Develop synthesizable RTL aligned with performance, power, and area targets
• Execute RTL quality checks including lint, CDC, and low-power verification
• Support integration, debugging, and design validation activities
• Collaborate with senior engineers across design and verification teams

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field
• 3+ years of experience in digital design or RTL development
• Strong understanding of RTL development flow including Lint, CDC, and CLP
• Experience with scripting languages such as Perl, TCL, or Python
• Solid understanding of ASIC design fundamentals

Preferred Qualifications

• Exposure to subsystem integration or SoC environments
• Familiarity with synthesis and timing concepts

Why Join Us

• Work on cutting-edge semiconductor technologies and complex silicon programs
• Collaborate with globally distributed engineering teams
• Opportunity to influence architecture and product innovation
• Culture focused on technical excellence, ownership, and continuous learning