ASIC RTL Design Architect

ASIC RTL Design Architect

Location: Bengaluru

Experience: 10–16 Years

About the Role

We are seeking an experienced ASIC RTL Design Architect to drive the architecture, microarchitecture, and RTL implementation of next-generation SoCs targeting AI/ML, Data Center, Networking, Storage, and High-Performance Computing applications. The ideal candidate will combine deep architectural thinking with hands-on RTL design expertise and a proven track record of delivering complex silicon products from concept to tape-out.

Key Responsibilities

• Define and own the architecture and microarchitecture of complex ASIC/SoC subsystems.
• Drive performance, power, area (PPA), scalability, and latency trade-offs.
• Architect high-performance datapaths, memory subsystems, cache hierarchies, interconnect fabrics, and hardware acceleration engines.
• Translate architectural specifications into high-quality RTL using Verilog/SystemVerilog.
• Lead design reviews, microarchitecture reviews, and technical decision-making across cross-functional teams.
• Collaborate closely with Verification, Physical Design, DFT, Firmware, and System Architecture teams to ensure successful silicon execution.
• Drive performance modeling, architectural analysis, debug, and silicon bring-up activities.
• Mentor senior engineers and provide technical leadership across the design organization.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
• 10–16 years of experience in ASIC/SoC RTL Design and Microarchitecture.
• Strong expertise in Verilog/SystemVerilog and digital design fundamentals.
• Proven experience delivering multiple successful silicon tape-outs.

Preferred Technical Expertise

• Strong expertise in Computer Architecture, Microarchitecture, and RTL Design for CPU, GPU, AI/ML Accelerators, DSP, or High-Performance SoCs.
• Hands-on experience in high-speed datapath design, pipelined architectures, cache/memory subsystems, NoC/interconnects, and hardware acceleration engines .
• Deep understanding of AMBA AXI/AHB/APB/CHI, PCIe, CXL, DDR/LPDDR/HBM, and high-speed interface protocols .
• Proficiency in Verilog/SystemVerilog and ASIC design methodologies including CDC/RDC, Lint, Formal Verification, UPF, Synthesis, and Timing Closure .
• Experience with performance modeling, architectural trade-off analysis, FPGA prototyping, emulation, and silicon bring-up .
• Proven track record of delivering multiple successful tape-outs in advanced technology nodes.

What We're Looking For

• Strong ownership mindset with the ability to solve complex architectural challenges.
• Ability to drive technical decisions across multiple engineering disciplines.
• Passion for building world-class silicon products and mentoring high-performing engineering teams.
• Excellent problem-solving, debugging, and communication skills.