100% Onsite
in San Diego, CA 92121
Initial assignment duration:
6 months (extension subject to performance and fit)
Job Description:
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SoC Power team is looking for ASIC engineers who will be responsible performing SoC level low power implementation working as part of the team.
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The person will require to validate SoC power intent spec using in house native tool (UPF generation) and use Cadence Conforml Low Power validation tool.
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Task includes defining low power requirements implementation of digital, mixed-signal circuits and systems that are integrated into System-on-Chip (SoC).
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As part of the SoC power team the you will be interfacing with frontend RTL, DFT, Synthesis, Design Verification and Physical Design teams during the SoC development.