Bootstrap

Google

ASIC Design For Testability CAD Engineer, Silicon

๐Ÿ“ŒBengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ senior

Minimum qualifications:

  • Bachelor's degree in Computer Science, Electronics or Electrical Engineering, or equivalent practical experience.
  • 5 years of experience in ASIC design for test including complete silicon life cycle through DFT pattern bring-up on ATE and manufacturing.
  • Experience with ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
  • Experience with DFT EDA tools (e.g., Tessent).

Preferred qualifications:

  • 8 years of experience with DFT Design or CAD.
  • Experience with DFT for subsystems with multiple physical partitions.
  • Experience with Spyglass-DFT, and DFT Scan constraints, and evaluating STA paths.
  • Experience in developing automated workflows using Python and Tcl.
  • Experience with workflows related to ATPG, Low Power designs, BIST, JTAG, IJTAG tools and flow.
  • Experience with DFT EDA tools like Tessent.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Work with a team of DFT engineers, RTL and Physical Designer Engineers.
  • Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains.
  • Write scripts to automate the DFT flow.
  • Develop tests that can be used for Production in the ATE flow.


Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Other similar jobs

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

CPU Physical Design Principal Engineer

@ Qualcomm, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Analog Design Engineer - REF79515L

@ Continental, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Staff Engineer, Digital IC Design

@ Marvell Technology, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Physical Design Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ senior

  • Skills
  • Industry
  • Find similar jobs

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    CPU Physical Design Principal Engineer

    @ Qualcomm, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Analog Design Engineer - REF79515L

    @ Continental, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    Staff Engineer, Digital IC Design

    @ Marvell Technology, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Physical Design Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—