ASIC Design Engineering Lead

Title : ASIC Design Engineering Lead

Location : San Jose, CA

Duration : 12+ Months

Rate : OPEN

Visa Status : USC/GC

In-Person Interview : No

Relevant Experience (in Yrs.) : 5+

Detailed Job Description:

Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips

· Design & implement robust and reusable RTL with CDC/RDC considerations

· Spec comprehensive CDC/RDC check flows and work with CAD team to implement

· Review and approve CDC/RDC constraints and waivers

· Perform static glitch analysis

Improve design with prevention of static glitch harzad

· Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design

· RTL development skills and experiences

· Solid understanding on CDC/RDC concepts and relevant design implementation

· Experience on maintaining CDC/RDC flow and signing-off constraints and waivers

· Solid understanding on static glitch harzads and experience on the relevant analysis on synthesis optimized gate netlists

Thanks, and Regards

Prasanna Kumar

Team Lead

Ascii Group LLC

Email: [email protected]

Phone: 13134350820/ (248) 476-7600 Ext 112