Bootstrap

Google

ASIC Design Engineer, RTL, Silicon

๐Ÿ“ŒBengaluru, India ๐Ÿ‡ฎ๐Ÿ‡ณ

โฑ๏ธŽ full-time

๐Ÿง™โ€โ™‚๏ธ mid-level

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
  • 3 years of experience in design, multi-power domains with clocking, and SoCs with silicon.
  • Experience with Verilog or SystemVerilog language.
  • Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Estimation.

Preferred qualifications:

  • Master's degree or PhD in Electrical Engineering or equivalent practical experience.
  • Experience with chip design flow and cross-domain involving DV, DFT, Physical Design, software.
  • Experience in STA closure, DV test-plan review and coverage analysis of the sub-system and chip level verification.
  • Knowledge in one or more of these areas: Processor Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Responsibilities

  • Define the microarchitecture of IPs, Subsystems or SOCs and work with the team to deliver a quality, schedule compliant and PPA optimized design.
  • Work with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.
  • Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
  • Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks.
  • Work with key design collaterals such as SDC and UPF, and with stakeholders to negotiate the right collateral quality and identify solutions.


Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Other similar jobs

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Senior ASIC Timing Engineer

@ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

CPU Physical Design Principal Engineer

@ Qualcomm, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Analog Design Engineer - REF79515L

@ Continental, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Staff Engineer, Digital IC Design

@ Marvell Technology, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Design Verification Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC Physical Design Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

ASIC RTL Engineer, Annapurna Labs

@ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

  • Employment

    โฑ๏ธŽ full-time

  • Experience

    ๐Ÿง™โ€โ™‚๏ธ mid-level

  • Skills
  • Industry
  • Find similar jobs

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    Senior ASIC Timing Engineer

    @ NVIDIA, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    CPU Physical Design Principal Engineer

    @ Qualcomm, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Analog Design Engineer - REF79515L

    @ Continental, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    Staff Engineer, Digital IC Design

    @ Marvell Technology, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Design Verification Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC Physical Design Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

    ASIC RTL Engineer, Annapurna Labs

    @ Amazon, ๐Ÿ“India ๐Ÿ‡ฎ๐Ÿ‡ณ

Remote Work
Post time
Level
Employment
Industry
Apply Now โ†—