ASIC DESIGN FOR TEST ENGINEER - Acacia
📌Austin, United States 🇺🇸
⏱︎ full-time
🧙♂️ senior
Meet the Team
Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group.
Your Impact
As a member of Acacia’s ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
- You will work with seasoned DFT engineers to implement and verify Design For Test.
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You will also interact with RTL/PD/STA/ATE, collaborating with them for a successful tape out.
- Typically: Bachelors + 7 years of related experience, or Masters +4 years of related experience, or PHD + 1 years of experience in ASIC DFT flows and implementation.
- Prior experience implementing scan control logic in RTL
- Prior experience with hierarchical ATPG and core wrapping techniques, ATPG and post-silicon DVT
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Prior experience with Synopsys/Mentor DFT tools
- Experience with scan compression and scan partitioning
- Experience with MemoryBIST, eFuse, Repair and yield improvement techniques
- Experience with JTAG Boundary Scan Insertion AC/DC
- Experience with Clocking architecture during various ATPG modes such as: Intest and Extest
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TCL scripting experience to automate DFT flows
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
Senior Embedded Software Engineer
@ Embedd 
What we're looking for
At embedd.it, we power hardware-software integration in embedded devices. We turn fragmented semiconductor chip data into configurable digital twins, then deterministically generate code, tests, and documentation – making integration faster, cheaper, and resilient to supply chain shocks.
We’re looking for a true legend – someone with abstract thinking and deep expertise in low-level software development. You’ll build vendor-agnostic tooling for MCU and peripheral integration to solve hardware-software integration once and for all. We work at the intersection of embedded systems, code generation, compilers, and machine learning. It’s your chance to help redefine how low-level development is done.
Responsibilities
- Drive the architecture of the driver structures and system layout
- Define scalable patterns for cross-architectural integration across bare-metal, Zephyr, Linux, and other environments
- Deconstruct complex SoC device trees and translate hardware descriptions into structured internal models for automated reasoning
- Partner with the ML team to shape data and annotation models for AI-driven data-extraction tooling
Qualifications
- 5+ years of experience in embedded systems development, including bare-metal and RTOS-based systems
- Proficiency in C/C++
- Familiarity with firmware configuration, SoC bring-up, and system-level debugging
- Hands-on experience with code generation tools, or low-level compiler/decompiler/emulator technologies
- Strong background in embedded toolchains: compilers, linkers, debuggers, and build systems
- Python or scripting for automation and tooling is a plus
- Experience with functional-safety standards is a plus
Why embedd.it?
- Dynamic, venture-backed team of engineers challenging the status quo 🚀
- Work at the intersection of embedded systems, code generators, compilers, and ML 🤖
- Unusual challenges requiring out-of-the-box abstract thinking 🧠
- Competitive compensation: cash + equity 💰
- Remote work possible 🌍
About Us
embedd.it is a UK-based startup reinventing embedded development. Our platform transforms unstructured semiconductor data into structured digital twins, enabling automatic generation of drivers, tests, and documentation. We're building a single, traceable source of truth to make integration fast, vendor-agnostic, and future-proof.
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Employment
⏱︎ full-time
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Experience
🧙♂️ senior
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Skills
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Industry
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