Job description:
In this role, you will be responsible for defining, implementing, and optimizing digital logic designs at the Register Transfer Level (RTL) for complex ASIC/SoC systems.
You will work closely with architecture, verification, physical design, and validation teams to deliver high-performance, power-efficient, and functionally robust designs.
Responsibilities:
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Translate architectural specifications into efficient and synthesizable RTL designs (SystemVerilog).
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Develop detailed microarchitecture specifications for functional blocks or subsystems.
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Integrate IP blocks and ensure seamless connectivity and data flow across the SoC.
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Run design checks (lint, CDC, synthesis readiness) and support backend implementation.
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Collaborate with verification teams to define test plans, review coverage, and debug design issues.
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Support validation and bring-up teams during silicon bring-up and debug phases.
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Optimize designs for power, area, and timing while maintaining functional integrity.
Profile description:
Requirements:
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B.Sc./M.Sc. in Electrical Engineering, Computer Engineering, or related field.
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3+ years of experience in digital logic or RTL design for ASIC/SoC projects.
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Strong proficiency in SystemVerilog.
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Solid understanding of digital design fundamentals (FSMs, pipelining, arbitration, clock/reset domain handling, etc.).
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Experience with EDA tools for simulation, synthesis, and linting (e.g. Synopsys, Cadence, Mentor).
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Familiarity with low-power design techniques, timing analysis, and interface protocols (e.g., AXI, AMBA, PCIe, DDR).
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Excellent problem-solving skills, attention to detail, and ability to work in a cross-functional environment.
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Experience with SoC-level integration and debug. - Advantage.
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Knowledge of scripting languages (Python, Perl, or Tcl) for automation. - Advantage.
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Exposure to FPGA prototyping or emulation environments. - Advantage.
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Understanding of hardware/software interaction and system-level architecture. - Advantage.
Why should you join us?
We offer:
Why should you join us?