TPU Compute RTL Design Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 8 years of experience with digital design using SystemVerilog RTL.
• Experience with power, performance and area optimizations.

Preferred qualifications:

• Experience interacting with software, architecture, physical design and other cross-functional teams.
• Knowledge of processor design, accelerators, or memory hierarchies.

About the job:

As an ASIC Design Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.

Responsibilities:

• Work independently to create and review the compute subsystem's design microarchitecture specifications.
• Define compute subsystem integration requirements to the SOC.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with design validation (DV) teams to create testplans to verify, and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.