Key Skills
RTLASICSoCVerilogSystemVerilog
Industry
SemiconductorConsumer Electronics
Job Description
Title:
Sr. RTL Designer
Industry: Silicon Engineering
Location: San Jose, CA
Duration: 6 months+
Responsibilities
ref_id: 79d09142-de41-4ac0-8361-e57880587a74
Industry: Silicon Engineering
Location: San Jose, CA
Duration: 6 months+
Responsibilities
- Develop microarchitecture and design specifications for digital blocks and SoC subsystems
- Write, optimize, and maintain RTL in Verilog and SystemVerilog
- Design high-speed datapath, control, and interface logic for complex ASICs
- Support high-speed I/O subsystems such as PCIe, UCIe, CXL, or similar interfaces
-
Develop models, assertions, and testbench components to support verification
- BS or MS in Electrical Engineering, Computer Engineering, or a related field
- 5+ years of ASIC, SoC, or digital design experience
- Strong experience writing synthesizable RTL in Verilog and SystemVerilog
- Experience owning digital blocks from specification through implementation
-
Strong understanding of high-speed digital design and timing-sensitive logic
- RTL Design
- ASIC
- SoC
- Verilog
- SystemVerilog
- Digital Design
- High-speed I/O
- Timing Closure
- Silicon Debug
-
Python
ref_id: 79d09142-de41-4ac0-8361-e57880587a74
Featured Opportunities
Companies Hiring RTL Design Engineer
Key Skills
RTLASICSoCVerilogSystemVerilog
Industry
SemiconductorConsumer Electronics
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