Senior Toolchain Engineer, Firmware

About Grafton Sciences

We’re building AI systems with general physical ability — the capacity to experiment, engineer, or manufacture anything. We believe achieving this is a key step towards building superintelligence. With deep technical roots and real-world progress at scale (e.g., a $42M NIH project), we’re pushing the frontier of physical AI. Joining us means inventing from first principles, owning real systems end-to-end, and helping build a capability the world has never had before.

About The Role

We’re seeking a Firmware/HDL Automation Lead Engineer to build a fully automatic pipeline for generating firmware and HDL (e.g., Verilog/SystemVerilog) that runs a control console for real hardware systems. You’ll sit at the intersection of digital design/verification and agentic LLM pipeline engineering , turning specs into structured representations, generating deterministic RTL/firmware, and closing the loop with tool-driven validation (synth/sim/formal) until the system is correct, robust, and reproducible.

This role is ideal for someone who can design production-grade RTL and verification, understands FPGA/ASIC constraints deeply, and can build automation systems that are safe, testable, and reliable enough to trust with real hardware control logic.

Responsibilities

• Design and implement auto-generation flows that transform control-console specs into structured IR/DSL and then into deterministic firmware + RTL (Verilog/SystemVerilog), including register maps, FSMs, and memory-mapped control/status interfaces.
• Own digital design correctness end-to-end: clock/reset domains, CDC strategy, timing/constraints, synthesis- and implementation-aware RTL, and timing closure readiness (FPGA and/or ASIC-style flows).
• Build and maintain integration layers for common buses and protocols (UART/SPI/I2C/CAN/Ethernet) and internal fabrics (AXI/APB/Wishbone), including clean memory-mapped control/status architectures.
• Develop verification infrastructure: self-checking testbenches, assertion-based verification (SVA), linting, coverage-driven regression, and formal methods where applicable.
• Implement tool-driven feedback loops that run synth/sim/formal (e.g., Verilator/ModelSim-class simulators; formal where possible), parse failures deterministically, and automatically propose/patch fixes with clear traceability.
• Ship CI/CD and regression systems for generated artifacts: golden tests, build determinism, reproducible tool runs, artifact provenance, and “no silent changes” guardrails.
• Add safety/security guardrails for generated control logic: invariants, forbidden-state constraints, privilege boundaries, safe default states, audit logging, and policies that prevent unsafe or irreproducible outputs from entering production.
• Collaborate closely with platform, ML/agent teams, and domain experts to integrate the pipeline into real workflows and hardware programs.
  
  

Qualifications

• Strong digital design experience: FSM design, register maps, timing/constraints, clock/reset domain design, CDC fundamentals, and debug in simulation and on hardware.
• Experience integrating hardware protocols/buses, including memory-mapped control/status patterns and practical bring-up considerations.
• Solid verification background: self-checking testbenches, SVA/assertions, familiarity with UVM concepts, linting, and comfort using simulation tools (e.g., Verilator and commercial simulators). Formal experience is a plus.
• Practical understanding of FPGA and/or ASIC flows and what it takes to deliver synthesizable, timing-clean, integration-ready RTL.
• Proven ability to build reproducible automation pipelines: deterministic codegen, structured interfaces, error parsing/classification, regression testing, and CI/CD.
• Experience with agentic LLM pipeline engineering: spec → structured IR/DSL, deterministic templating/codegen, tool-calling loops, and robustness/safety mechanisms that keep automated generation correct and auditable.
• Strong software engineering fundamentals (clean architecture, testing discipline, versioning/provenance, reliability mindset).
  
  

Above all, we look for candidates who can demonstrate world-class excellence: rigorous engineering judgment, deep ownership, and the ability to build systems that are both powerful and safe to trust .

Compensation

We offer competitive salary, meaningful equity, and benefits.