Senior SoC Design Verification

Greetings!!!

Role:- Senior SoC Design Verification

Location-Hyderabad (Hybrid)

Duration: Contract to Hire

Immediate Joiner

Experience Level: 5+ yrs

Skills:

Strong hands-on expertise in System Verilog and UVM.

Solid understanding of verification methodologies, constrained-random testing, assertions, and coverage-driven verification.

Experience with SoC fabrics and standard protocols such as AXI, AHB, APB, NoC, PCIe, USB, Ethernet, DDR, CXL, CHI, ACE, or similar, depending on domain.

Experience in subsystem integration verification including resets, clocks, interrupts, boot flows, power states, and register validation.

-Refer and earn Rs.50,000/-

-Check global opportunity at IITJOBS

If you are interested , please share your resume to [email protected]