Senior SoC Design Verification Engineer

About the Role

We are seeking an experienced Senior SoC Design Verification Engineer to join a high-performing semiconductor team working on next-generation SoC products. The ideal candidate will have strong expertise in SystemVerilog , UVM , and SoC verification , along with proven experience developing scalable verification environments and driving verification closure for complex ASIC/SoC designs.

This is a hands-on role requiring strong technical leadership, debugging skills, and the ability to collaborate effectively with cross-functional engineering teams.

Key Responsibilities

• Develop and execute verification plans for complex SoC and subsystem-level designs.
• Design, develop, and maintain robust UVM-based verification environments.
• Create reusable verification components, testbenches, sequences, scoreboards, monitors, and coverage models.
• Verify functionality at IP, subsystem, and full-chip SoC levels.
• Integrate and configure industry-standard Verification IP (VIP).
• Develop constrained-random and directed test scenarios to improve coverage and verification quality.
• Analyze simulation results, debug functional issues, and work closely with design teams to resolve defects.
• Drive functional and code coverage closure.
• Support verification infrastructure development, regression automation, and continuous integration efforts.
• Collaborate with architecture, design, firmware, and validation teams throughout the product development lifecycle.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of ASIC/SoC Design Verification experience.
• Strong hands-on experience with SystemVerilog .
• Strong expertise in UVM (Universal Verification Methodology) .
• Proven experience in SoC verification and integration-level verification.
• Strong debugging, analytical, and problem-solving skills.
• Excellent communication and collaboration skills.
• Ability to work onsite in Santa Clara, CA.

Preferred Qualifications

• Experience with system-level or full-chip verification.
• Strong understanding of AXI4 and related protocols.
• Experience with scripting languages such as Python , Perl , or Shell .
• Proficiency in C programming .
• Experience developing verification infrastructure and automation frameworks.
• Familiarity with testbench architecture, VIP integration, and regression management.

Required Skills

• SoC Design Verification
• SystemVerilog
• UVM
• AXI4
• Testbench Development
• VIP Integration
• Functional Coverage
• Debugging & Problem Solving

Nice-to-Have Skills

• Python
• Perl
• Shell Scripting
• C Programming
• System-Level Verification
• Regression Automation
• Verification Infrastructure Development