Senior RTL Design Engineer

• Perform RTL coding, conduct code reviews, and debug designs.
• Work with third-party vendors to procure and integrate the Ethernet block with MAC, PCS, and PHY.
• Partner with Verification Engineers to define the test plan, execute verification, and understand both serial and parallel mode VIP behavior.
• Debug the full Ethernet protocol stack.

Qualifications

• Proven record of successful tape-outs and productization, preferably in networking devices.
• Strong understanding of the Ethernet.
• Comprehensive understanding of multiple clock, reset, and power domain design challenges with safe/robust design practices.
• Excellent knowledge of industry-standard tools and best-in-class practices for high-quality design.
• Prior experience with source synchronous design implementation.
• Essential knowledge of Ethernet architectures and Layer 2, Layer 3, and Layer 4 networking protocols.
• Prior experience in integrating a MAC IP with PCS and SerDes PHY, preferably at 100G or higher.Ethernet PCS IP integration experience for 100Gbps or higher would have been reasonable.
• Phy And D2D adapter experience is needed.