Senior Hardware & Firmware Engineer

Vizwise Analytics 

📍 Dallas, United States 🇺🇸

full-time
senior
hybrid
Posted —

Key Skills

C/C++FPGASoCNVMeTPM

Industry

DefenseConsumer Electronics

Job Description


Location: Houston, Texas (On-site / Hybrid)

Position Type: Full-time (Anticipated opening upon program funding)

Citizenship: U.S. Citizenship Required (ITAR / Export-Controlled)

About the Role

Digital Archives Pro is developing DAP-VAULTIS , a hardware-grounded, data-centric security engine for tactical-edge and air-gapped environments supporting U.S. Navy and DoD mission needs.

As a Senior Hardware & Firmware Engineer , you will own the low-level hardware and firmware execution of our storage-controller platform, bridging high-level architecture with physical hardware realization.

Key Responsibilities
  • Firmware & Drivers: Develop register-level firmware and device drivers (C/C++) for the DAP Storage Controller (DSC).
  • Storage Control: Implement bus-level command handling, write-protect/WORM enforcement logic, and physical I/O suppression.
  • Hardware Bring-Up: Validate and debug evaluation boards, FPGA/SoC platforms, and secure storage microcontrollers.
  • Security Integration: Integrate secure elements (HSMs, TPMs, monotonic counters, crypto-coprocessors) into the firmware stack.
  • HIL Testing: Design and run hardware-in-the-loop (HIL) test plans; analyze timing, latency, and fault-injection behavior.
RequirementsMust-Haves:
  • U.S. Citizenship (Strictly required for ITAR/export control).
  • Education: B.S. in Electrical Engineering, Computer Engineering, or related field.
  • Experience: 5+ years in embedded systems and firmware engineering.
  • Skills: Expert-level C/C++ for register-level driver development and low-level hardware debugging.
  • Tech: Hands-on experience with storage/peripheral bus protocols and board-level validation.
Great-to-Haves (Preferred):
  • Experience with NVMe, eMMC, or UFS storage-controller interfaces.
  • Experience with FPGAs / SoCs (e.g., Xilinx Zynq, PolarFire SoC) and VHDL/Verilog .
  • Experience integrating TPM 2.0 or ATECC608 secure elements.
  • Active or eligible for a U.S. Security Clearance (Secret or higher).


Thanks & Regards,

D Diny

[email protected]