Senior FPGA Engineer

Logica-IT โ†—

๐Ÿ“ Holon, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ

full-time
senior
Posted โ€”

Key Skills

FPGAVHDLVerilogXilinxIntel

Industry

SemiconductorConsumer Electronics

Job Description


ืื ื—ื ื• ืžื—ืคืฉื™ื ืžื”ื ื“ืก/ืช FPGA ืœืคื™ืชื•ื— ืžืขืจื›ื•ืช ืœื•ื—ืžื” ืืœืงื˜ืจื•ื ื™ืช

ืžืฉืจื” ืžืœืื” ื‘ื—ื•ืœื•ืŸ

ื”ื–ื“ืžื ื•ืช ืœืงื—ืช ื—ืœืง ื‘ืคื™ืชื•ื— ื”ื“ื•ืจ ื”ื‘ื ืฉืœ ืžืขืจื›ื•ืช EW, ืžืฉืœื‘ ื”ืงื•ื ืกืคื˜ ื•ืขื“ ื™ื™ืฆื•ืจ ื•ืคืจื™ืกื” ืžื‘ืฆืขื™ืช.


ืžื” ืชืขืฉื• ืืฆืœื ื•?

ืคื™ืชื•ื—, ืกื™ืžื•ืœืฆื™ื” ื•ื™ื™ืฉื•ื ืฉืœ ืจื›ื™ื‘ื™ FPGA ืœืžืขืจื›ื•ืช ืœื•ื—ืžื” ืืœืงื˜ืจื•ื ื™ืช.

ืชื›ื ื•ืŸ RTL ื‘ึพVHDL/Verilog.

ืขื‘ื•ื“ื” ืขื ื›ืœื™ ืคื™ืชื•ื— ืฉืœ Xilinx/AMD ืื• Intel/Altera.

ื›ืชื™ื‘ืช Testbenches ื•ื‘ื™ืฆื•ืข ืกื™ืžื•ืœืฆื™ื•ืช ื‘ึพModelSim/Questa.

ื ื™ืชื•ื— ืชื–ืžื•ื ื™ื, CDC, STA ื•ึพtiming closure.

Debug ื‘ืžืขื‘ื“ื” ืขื ILA/ChipScope/SignalTap.

ืื•ืคื˜ื™ืžื™ื–ืฆื™ื” ืฉืœ ืžืฉืื‘ื™ื, FSMs, pipelines ื•ึพDSP.

ืฉื™ืžื•ืฉ ื‘ืกืงืจื™ืคื˜ื™ื (Python/Tcl/Bash) ืœืื•ื˜ื•ืžืฆื™ื” ืฉืœ ืชื”ืœื™ื›ื™ ืคื™ืชื•ื—.


ื“ืจื™ืฉื•ืช ื—ื•ื‘ื”

ืชื•ืืจ ืจืืฉื•ืŸ ื‘ื”ื ื“ืกืช ื—ืฉืžืœ/ืžื—ืฉื‘ื™ื/ืืœืงื˜ืจื•ื ื™ืงื”.

5 ืฉื ื•ืช ื ื™ืกื™ื•ืŸ ื‘ืคื™ืชื•ื— FPGA.

ืฉืœื™ื˜ื” ื‘ึพVHDL/Verilog.

ื ื™ืกื™ื•ืŸ ืขื Vivado / Quartus ืื• ื›ืœื™ื ืžืงื‘ื™ืœื™ื.

ื ื™ืกื™ื•ืŸ ื‘ืกื™ืžื•ืœืฆื™ื” ื•ื›ืชื™ื‘ืช Testbenches.

ื”ื‘ื ื” ืžืขืžื™ืงื” ืฉืœ STA, CDC ื•ืชื–ืžื•ื ื™ื.

ื ื™ืกื™ื•ืŸ ื‘ึพdebug ืขืœ FPGA.

ื™ื›ื•ืœืช ืขื‘ื•ื“ื” ื‘ืฆื•ื•ืช, ื ื™ื”ื•ืœ ืžืฉื™ืžื•ืช, ื•ืขืžื™ื“ื” ื‘ืœื•ื—ื•ืช ื–ืžื ื™ื.


ื™ืชืจื•ืŸ ืžืฉืžืขื•ืชื™

ื ื™ืกื™ื•ืŸ ื‘ืื•ื˜ื•ืžืฆื™ื” ื•ืกืงืจื™ืคื˜ื™ื.

ืขื ื™ื™ืŸ ื‘ื˜ื›ื ื•ืœื•ื’ื™ื•ืช AI ื•ืคืชืจื•ื ื•ืช FPGA ืžืชืงื“ืžื™ื.