Senior DSP and ASIC Engineer

This is an Engineering position for High Speed Interconnect Products (HSIP).

Broadcom has the most extensive physical layer product portfolio in the industry including 800-Gigabit Ethernet Copper and Optical PHYs, Backplane SerDes, and Optical Transport. Broadcom's proven PHY technology offers lower power with a smaller footprint, as well as proven interoperability and advanced features, making it easier and less expensive to build an array of networking equipment, including telecommunications chassis, switches, routers, hubs and more.

In this role you will join a team of highly skilled designers involved in design, modeling, verification, and firmware development for the physical layer of high speed SerDes at speeds of 112Gbps and above with both analog and digital components.

Job Description

Looking for a design engineer to work on challenging high speed design of complex modules for Ethernet and PCIE cores used across multiple chips. You will be responsible for the modeling and simulations of DSP algorithm and implementation from system spec, verifying the hardware implementation, software co-development and verification. The job is on site. Locations are flexible: San Jose or Irvine, California; or Austin, Texas.

Job Requirements:

• A Bachelor’s Degree in Electrical and Electronic Engineering or Computer Science with 8+ years relevant industry experience, or a Masters degree in Electrical and Electronic Engineering or Computer Science with 6+ years relevant industry experience.
• Experience with digital signal processing.
• Fluent in C++.
• Demonstrate the ability to work through technology challenges and physical implementation issues associated with high-performance design implementations.
• Additionally, the candidate should possess excellent communication and inter-personal skills to work closely with other team members and demonstrate an ability to learn new tools quickly.
• Must have legal authorization to work in the US.

The candidate should have expertise in some of the following areas:

• Digital signal processing knowledge.
• Experience working with high speed silicon designs. Post silicon bring up experience is desirable.
• Extensive experience with C++. Experience in Verilog is desirable but not necessary.
• Extensive use of Matlab, Perl, Python or other scripting languages.
• Familiarity with digital chip design concepts, such as clocking, timing, pipelines, and performance vs area/power tradeoffs.