Senior Chip Design Engineer, RTL

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Senior Chip Design Engineer, RTL

Chipmind Zurich, Switzerland

Senior Chip Design Engineer, RTL

Chipmind Zurich, Switzerland

2 days ago 26 applicants

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Harald Kröll, PhD

Harald Kröll, PhD

CEO at Chipmind 🐿️

About Chipmind

Chipmind is an AI-native company, transforming chip development with Agentic AI that automates design and verification by solving real-world tasks, accelerating the path from code to chip.

Role Description

Join Chipmind as a Senior Chip Design Engineer and play a pivotal role in shaping the next generation of AI-assisted EDA tools for digital chip design and verification. We're looking for someone who has been “in the trenches” – someone who understands the real-world frustrations and complexities of RTL design and is eager to work on solutions to tackle them. In this role, you won’t be designing chips the traditional way. You will work on a broad spectrum: One one hand you will contribute to the development of our agentic chip design solution by using your hands-on experience with RTL design and across the RTL-to-GDS flow. On the other hand you will design new and improve existing RTL blocks which are key for the evaluation and integration of our agentic solution and support the software development. You will work on intelligent tools that make digital design faster, more reliable, and more enjoyable in a highly skilled team of ML engineers and chip design engineers. Your expertise and insights will make a tangible impact in a fast-paced, innovative AI startup!

What We Offer

• A unique opportunity to shape the future of AI-assisted RTL design tools by applying your real-world experience.
• Direct influence on product direction and tool capabilities, working closely with software and AI experts.
• A dynamic and agile work environment with significant autonomy and creative input.
• A collaborative team that values practical insight as much as technical innovation.
• An office in the vibrant Zurich Wiedikon district, with the energy of a fast-paced startup and the focus of a deep-tech company.
  
  

Responsibilities

• Use your hands-on RTL design experience to evaluate, challenge, and improve our AI-driven EDA tools.
• Implement, develop and optimize our agentic chip design solution.
• Help integrate the EDA tool chain across the RTL-to-GDS flow, including simulation, synthesis, static timing, and PnR - both commercial and open-source.
• Design representative RTL scenarios and tasks collaborate closely with software and AI engineers to bridge the gap between cutting-edge algorithms and practical design tasks.
• Help define and prioritize features that truly matter to digital designers.
  
  

Qualifications

• 3+ years of hands-on experience in digital RTL design using SystemVerilog, including simulation, debugging, and design closure.
• Solid understanding and practical experience in the entire commercial digital design flow from RTL to GDS.
• Strong intuition for common design pain points, inefficiencies, and edge cases, with a desire to improve the design experience.
• Strong interest in AI and EDA innovation, comfortable collaborating with software engineers and ML researchers, to shape the product definition.
• Working knowledge of Python
  
  

Nice to have

• Experience with the open-souce EDA tools
• Experience with VHDL
• Seniority level Mid-Senior level
• Employment type Full-time
• Job function Engineering and Information Technology
• Industries Semiconductor Manufacturing
  
  

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