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Vantage

Senior ASIC Physical Design / Backend Engineer

Vantage

📍 Stockholm, Sweden 🇸🇪

full-time
senior
140000
hybrid
Posted —

Key Skills

ASICRTLtimingCadenceSynopsys

Industry

SemiconductorAutomotive

Job Description

Senior ASIC Backend Engineer (Physical Design) — Janus AI Safety Chip

Location: Stockholm or remote in EU/UK time zone

Reports to: CTO

Start: Within 60 days

Equity: 0.4%–1.2% with 4-year vest, 1-year cliff

Cash: €140K–€180K base depending on location and seniority


The opportunity


We are taking the Janus Verification Core from verified RTL through synthesis, place-and-route, timing closure, and tape-out on a EUROPRACTICE 28nm shuttle in 2027. We work with Alchip or GUC as our primary design house — you will be our internal counterpart, owning the backend flow on our side, making the architectural decisions that determine power, area, and yield. You will see this chip from RTL to packaged silicon to first bring-up.


What you'll do


Own the synthesis flow (Genus or Design Compiler) for the JVC RTL. Drive physical implementation through Innovus or ICC2 in partnership with our design house. Close timing at 2.5 GHz across all corners. Make the floorplan, clock tree, and power grid decisions that determine whether we yield on first silicon. Lead the DFT insertion (scan, MBIST, boundary scan). Coordinate signoff (STA, LVS, DRC, ERC, EMIR) for the EUROPRACTICE shuttle deadline.


What you bring


8+ years of physical design experience with at least one 28nm or smaller production tape-out. Deep familiarity with Cadence or Synopsys flows. Experience coordinating with a design house (Alchip, GUC, Faraday, eInfochips, or equivalent). Comfortable making architectural trade-offs without waiting for permission. Track record of closing timing on aggressive frequency targets.


What we don't want


Backend engineers who have only done block-level work. Anyone who needs the design house to make decisions on their behalf. Engineers whose tape-out experience is more than five years old.


The honest pitch


This is the role that makes or breaks the company. RTL bugs can be patched in a respin. Physical design mistakes mean silicon scrap and 12 months lost. You will have direct authority over the technical decisions that determine whether Janus exists. Equity is sized accordingly.


Apply with: CV, a list of tape-outs with process node and frequency, and one paragraph on a physical design trade-off you made that turned out to be right.