RTL/FPGA Design Architect

We are seeking an experienced RTL/FPGA Design Architect to drive the architecture, micro-architecture definition, and RTL implementation of high-performance networking and communication IPs. The ideal candidate will have extensive experience in FPGA design, networking protocols, PCIe architectures, and high-speed Ethernet solutions.

• Define micro-architecture and develop high-quality RTL designs for networking and communication IPs.
• Architect and design Network Interface Card (NIC) controllers, including datapaths, control structures, and interfaces.
• Develop synthesizable RTL using Verilog/SystemVerilog for networking protocols and high-speed interfaces.
• Design and optimize solutions for PCIe Gen4/Gen5, Ethernet MAC, TCP/IP offloading, NVMe over Fabrics, and related technologies.
• Maximize throughput and minimize latency for high-speed interfaces (100G Ethernet and above).
• Collaborate with software teams to define driver interfaces, APIs, and DPDK/SPDK integration.
• Create architecture documents, design specifications, and implementation plans.
• Perform RTL development, synthesis, timing closure, FPGA implementation, and validation.
• Support subsystem integration, lab bring-up, debugging, and unit test validation.
• Work closely with hardware, software, diagnostics, signal integrity, and verification teams.

• 14+ years of experience in FPGA architecture, RTL design, and digital design.
• Strong experience in NIC architecture and networking subsystem design.
• Deep understanding of L2/L3/L4 networking protocols.
• Expertise in PCIe Gen4/Gen5 and AXI/AMBA bus architectures.
• Strong hands-on experience with Verilog, VHDL, and SystemVerilog.
• Experience with high-speed Ethernet designs (100G+).
• Experience with FPGA platforms from Xilinx, Intel/Altera, and Microsemi.
• Proficiency with FPGA development tools such as Vivado, Quartus, and Libero.
• Strong understanding of Ethernet-based protocols, memory architectures, and high-speed interfaces.
• Experience with synthesis, timing closure, FPGA validation, and hardware bring-up.
• Familiarity with Unix/Linux environments and scripting tools.

• Experience with DPDK/SPDK integration.
• Knowledge of driver development and API design.
• Experience in hardware-software co-design and system-level optimization.
• Scripting experience using Python, Tcl, Shell, or Perl.