RTL Engineer

Responsibilities

• Contribute to FPGA and system architecture for on-board processing and
  
  

sensors/actuators control.

• Design and implement custom FPGA IP cores for data acquisition and control logic.
• Develop RTL in Verilog/SystemVerilog and perform synthesis, timing closure, and FPGA
  
  

build flows.

• Work with embedded Linux environments using Yocto or PetaLinux for SoC-based FPGA
  
  

systems.

• Enable processor ↔ FPGA integration using interfaces such as AXI/APB.
• Work with Xilinx or Microchip SoC platforms during bring-up and integration.
• Develop embedded C/C code for FPGA interface, control, and data handling.
• Perform testbench-level validation and system-level debugging.
• Support cross-functional hardware-software integration.
  
  

Required Experience & Skills

• 3 to 4 years of experience in FPGA or SoC-based embedded design.
• Experience with Verilog and/or SystemVerilog.
• Experience with FPGA IP core development.
• Experience working with Xilinx or Microchip SoCs (e.g. Zynq, Zynq Ultrascale+, PolarFire
  
  

SoC.

Familiarity with AXI, AXIStream, AXILite or similar processor-interconnect protocols.

Experience with Yocto or PetaLinux build environments.

Understanding of aarch64 ARM or RISCV based SoC architecture.

Experience with processorFPGA communication.

C/C development for embedded platforms.

Good to Have

• Experience with Linux system bring-up on SoCs.
• Exposure to device tree configuration and Linux driver integration.
• Experience using FPGA debugging tools and in-system analyzers.
• Familiarity with interface protocols SPI, I2C, UART, LVDS, Ethernet, SpaceWire).
• Exposure to system on chip bring-up and firmware integration.
• Experience with test and debug tools such as oscilloscopes, protocol analyzers, and JTAG.
  
  

Responsibilities & Duties

• Participate in next-generation system architecture – a full system effort spanning mission
  
  

planning, software, hardware, and other sub-systems.

• Develop custom IP for new features of the Pixxel camera payload and satellite bus.
• Understand the design requirements, establish the design infrastructure, support
  
  

verification engineers, and test the correctness of the design.

• Realize high-reliability digital design targeting state-of-the-art Xilinx FPGAs.
• Participate in conceptual design studies of new spacecraft.
  
  

Desirable Skills & Certifications

• Comfortable working with Xilinx Vivado Design Suite.
• Experience with external memories SSD, FLASH, etc.); high-speed transceivers for
  
  

protocols such as PCIe, SATA; and memory-mapped interfaces such as AXI, Wishbone,

Avalon.

• Using advanced design methodologies like Hierarchical Design.
• Experience using lab equipment: high-speed oscilloscopes, logic and protocol analyzers,
  
  

spectrum analyzers, etc.

• Experience with schematic design and board bring-up is a plus point.
  
  

Would be great if you have

• A Bachelorʼs Degree in EE, CS or CE (or a related field) with at least 2 years of relevant
  
  

experience or an Advanced Degree Masters or PhD.

• Excellent knowledge of hardware description languages Verilog/System Verilog/VHDL.
• Strong understanding of computer architecture and logic design, and serial interfaces –
  
  

SPI, I2C, LVDS, etc.

• Solid understanding of timing principles, including clock domain crossing and timing
  
  

closure.

• Experience with FPGA tools (e.g Vivado) and HDL Simulation Tools ModelSim).
• Strong debugging and analytical skills.
• Strong communication skills and the ability to work in a small team are a huge plus.
• Solid programming skills C / C, Python, Matlab).
  
  

Skills: verilog,soc,fpga