RTL Design

We are currently hiring experienced professionals for RTL Integration/Microarchitecture and MIPI/DDR RTL Design roles for our Bangalore location.

JD 1 – RTL Integration & Microarchitecture Engineer

Experience: 5–12 Years | Location: Bangalore | Notice Period: Immediate to 30 Days

• Strong experience in RTL Integration, SoC/Sub-system integration, and Microarchitecture design.
• Hands-on expertise in Verilog/SystemVerilog RTL development and integration flows.
• Experience with AMBA protocols such as AXI/AHB/APB and multi-clock domain designs.
• Good understanding of SoC architecture, interconnects, clock/reset architecture, and low-power concepts.
• Experience in RTL quality checks including Lint, CDC/RDC, and synthesis analysis.
• Exposure to FPGA/ASIC front-end design flow, timing constraints, and STA concepts.
• Familiarity with tools such as SpyGlass, DC, VCS/Xcelium/Questa, Verdi, Vivado, or Quartus.
• Experience in debugging RTL integration issues and supporting verification teams.
• Knowledge of UPF, power gating, and low-power verification is an added advantage.
• Strong communication skills and ability to work with cross-functional teams.

JD 2 – RTL Design Engineer (MIPI/CSI/DSI/DDR/LPDDR)

Experience: 5–14 Years | Location: Bangalore | Notice Period: Immediate to 30 Days

• Strong experience in RTL Design using Verilog/SystemVerilog for ASIC/FPGA development.
• Hands-on experience with MIPI protocols including CSI and DSI interfaces.
• Good knowledge of DDR/LPDDR controller/interface design and integration.
• Experience in high-speed protocol integration, timing closure, and performance optimization.
• Understanding of AMBA AXI/AHB/APB bus protocols and SoC integration.
• Experience with RTL coding, simulation, debugging, Lint, CDC, and synthesis flows.
• Familiarity with tools such as VCS, Xcelium, Questa, SpyGlass, Vivado, and Design Compiler.
• Exposure to low-power design concepts, UPF, and multi-clock domain handling.
• Ability to debug complex RTL/design issues and collaborate with DV/PD teams.
• Excellent problem-solving and communication skills.

Interested can share resume to - [email protected]