RTL Design Leader

Responsibilities:

• Micro-architect and implement RTL for CPU subsystems, bus fabric, peripheral IPs, and AI/NPU blocks in SystemVerilog.
• Lead 9-person team: assign block ownership, enforce coding guidelines, review quality, and own schedule.
• Define RTL-to-synthesis handoff checklist: CDC/RDC lint, clock/reset strategy, UPF power intent, coverage closure.
• Drive AI/NPU micro-architecture: MAC datapath, weight-buffer, SIMD sizing, and memory bandwidth budgeting.
• Own DFT strategy (scan, MBIST, BIST, boundary scan) with Physical Design and Production test teams.
• Support Physical Design with SDC constraints, scan chains, and ECO implementation during closure.
• Review and approve micro-architecture specs; ensure traceability to the SoC architecture specification.

Requirements:

• Bachelor’s or Master’s in Electrical/Computer Engineering.
• 10+ years RTL design experience; 3+ years as team lead or senior RTL architect.
• Expert SystemVerilog — synthesizable RTL and SVA assertion writing.
• Deep knowledge of Arm Cortex-M/R, AMBA AXI/AHB/APB/CHI, and on-chip memory subsystems.
• Hands-on with EDA: Synopsys DC/Fusion Compiler or Cadence Genus; VCS or Xcelium for simulation.
• Experience with UPF power intent and multi-voltage/power-gated designs.
• Solid DFT: scan insertion, ATPG, MBIST, boundary scan flows. Good English and Vietnamese skills.

Nice to Have:

• AI/NPU accelerator RTL: MAC arrays, systolic architectures, on-chip weight buffers.
• RTL design experience for Camera SoC: ISP pipeline, DSP, MIPI CSI-2 receiver, or video codec (H.264/H.265).
• RISC-V custom IP or drone/UAV real-time control applications.

Benefits:

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive compensation package, aligned with capabilities and performance.
• Comprehensive benefits and welfare package (FPT Care, annual company trips, team building activities, annual health check-ups) in line with a large-scale corporation.
• Exposure to a diverse ecosystem across the semiconductor value chain, including PMIC, IP Solutions, Engineering Services, ATE & Packaging, Camera & Drone, and IoT Devices.
• Access to professional training and development programs within FPT Corporation.
• Working hours: 9:00 AM – 6:00 PM, Monday to Friday.

Contact point:

If you are interested in this position, please send your resume and cover letter to email: [email protected] (Ms. Thu Huong – Mobile phone: 036.390.4039).