RTL Design Engineer

RTL Design Engineer – Wireless SoC (Remote – PST)

Location: Remote (must be aligned with PST time zone / willing to work PST hours)

We are seeking an experienced RTL Design Engineer to work on next-generation wireless SoC development. The ideal candidate will design and implement high-performance digital blocks and work closely with architecture, analog/mixed-signal, and verification teams to deliver production-quality silico

n.
🔹 Required Ski

lls5+ years of hands-on RTL design experience (SystemVerilog / Veril

og)Strong understanding of micro-architecture and RTL implementation from sp

ecsExperience in DSP hardware implementation (filtering, FFT, et

c.)Knowledge of SoC design flows: CDC, power domains, timing constraints, formal verificat

ionExperience with synthesis, linting, simulation, and STA to

olsUnderstanding of DFT concepts (scan, BI

ST)Strong debugging and problem-solving ski

llsGood communication and ability to work in cross-functional te

ams
🔹 Key Responsibili

tiesDesign, implement, and verify digital blocks for wireless SoCs using SystemVerilog/Ver

ilogTranslate architectural and algorithmic specifications into synthesizable

RTLImplement DSP blocks such as filtering, FFT/IFFT, beamforming,

etc.Develop RTL for SoC components including interfaces, clock/reset, power management, and debug l

ogicWork with internal and external IP integration into chip-level des

ignsCollaborate with AMS teams on digital-analog interfaces, calibration logic, and control sys

temsDrive PPA (power, performance, area) optimization and support timing closure with backend t

eamsParticipate in design reviews, integration, synthesis, and timing closure activi

tiesSupport silicon bring-up and lab validation of digital subsys

tems


- Design Verification E

ngineerRole – Design Verification E

ngineerLocation – - Remote (must be aligned with PST tim

e zone)


Job Description and other

details –
We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generati

on silicon.Qual

ifications B.S. or M.S. in Electrical Engineering, Computer Engineering, or rel

ated field.3+ years of experience in ASIC/SoC ve

rification.Solid understanding of SystemVerilog, digital logic, and hardware verifica

tion flows.Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and cov

erage tool.Experience with test planning, testbench development, constrained-random testing, and coverag

e analysis.Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system

(ex: Git).
Respo

nsibilities Develop and execute verification plans for block-level, subsystem-level, and full-chip e

nvironments.Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and cove

rage models.Write SystemVerilog Assertions (SVA) and integrate formal verification where

appropriate.Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stres

s scenarios.Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to res

olve issues.Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure f

or sign-off.Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug

iterations.Participate in design reviews and microarchitecture