Key Skills
VerilogSystemVerilogUVMASICEDA
Industry
SemiconductorAerospace
Job Description
About The Job
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark , General Catalyst , Peter Thiel , Adam D'Angelo , Larry Summers , and Jack Dorsey .
Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week
Role Responsibilities
Must-Have
Mercor connects elite creative and technical talent with leading AI research labs. Headquartered in San Francisco, our investors include Benchmark , General Catalyst , Peter Thiel , Adam D'Angelo , Larry Summers , and Jack Dorsey .
Position: RTL Design Engineers
Type: Contract
Compensation: $100–$175/hour
Location: Remote
Duration: 3+ months
Commitment: 40 hours/week
Role Responsibilities
- Evaluate digital chip design workflows to enhance AI model training and evaluation.
- Design and verify RTL components using Verilog/SystemVerilog.
- Collaborate with architecture, verification, and implementation teams to improve model outputs.
- Develop reusable verification components and testbench infrastructure.
- Leverage LLM-based tools to accelerate chip design and verification processes.
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Work independently and asynchronously to meet project deadlines.
Must-Have
- 3–10 years of experience in digital RTL design or design verification.
- Strong proficiency in Verilog/SystemVerilog and UVM.
- Solid understanding of digital design fundamentals: FSMs, datapaths, pipelines, FIFOs, arbiters, clock/reset domains, bus protocols.
- Experience with ASIC design flows and common EDA tools.
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Ability to write clear design documentation and communicate technical tradeoffs.
- Knowledge of AMBA protocols (AXI, AHB, APB).
- Background in CPU, GPU/ML accelerator, networking, memory subsystem, PCIe/high-speed IO, SoC interconnect, low-power design.
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Exposure to formal verification or SV/UVM-based design verification.
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Week of 04/23; applications reviewed on a rolling basis.
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Hourly contractor, Paid weekly.
- Upload resume
- AI interview based on your resume
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Submit form
- For details about the interview process and platform information, please check: https://talent.docs.mercor.com/welcome
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For any help or support, reach out to: [email protected]
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Companies Hiring RTL Design Engineer
Key Skills
VerilogSystemVerilogUVMASICEDA
Industry
SemiconductorAerospace