RTL Design -Director

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

The Director-SoC Lead role is a structural requirement as we chart our path for our next-generation switch and IO chiplet programs that address the needs of AI and Data Centre SoCs.

This Director-level SoC Lead spans the continuum from high-level system architecture to micro-architectural partitioning and hands-on RTL direction. The mandate spans multi-million gate integration, IP dependency orchestration, synthesis convergence, and timing closure within highly constrained PPA envelopes. At these technology nodes, the architecture is inseparable from the physical reality choices made in topology, buffering strategy, clocking domains, or protocol partitioning, which directly determine feasibility. Only an SoC leader with deep exposure to complex IP optimization and full-chip convergence can prevent costly late-stage refactoring.

You will be part of the CSG team focused on Data Center innovation through next-gen architectures for Dragonfly which is Qualcomm's rack-scale Agentic AI platform, reshaping compute efficiency and scalability for the AI era .

• Define and defend architectural trade-offs

• Drive milestone discipline across design, verification, and physical implementation

• Assess cross-IP friction

• Mentor engineers on design-for-convergence principles

• Design knowledge on Ethernet switch and IO chiplet programs are strategically important.

• Experience in ultra-high bandwidth data processing space, where low-latency transport, scalable throughput, and energy-efficient data movement are distinct.

• Leadership in this space requires someone who has navigated the full design convergence cycle: Architecture → Micro-Architecture → RTL → Verification → Synthesis → Timing Closure.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.

Minimum Qualifications:

18+ years of solid experience in IP/SoC design and micro-architecture

• Good knowledge of Digital Design and RTL development

• Hands-on experience with SoC Design, Verilog RTL coding

Minimum requirement is Bachelor of Engineering however preferred is Masters of Engineering in Computer Science or Computer Engineering. PhD in Computer Science, Engineering, Information Systems, or related field and 18+ years relevant working experience, thereof 5+ years relevant management experience is welcome

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