Process Integration Development Engineer – Embedded Source/Drain Epitaxy Integration

About the job

Tata Electronics Private Limited (TEPL) is a greenfield venture of the Tata Group with expertise in manufacturing precision components.

Tata Electronics (a wholly owned subsidiary of Tata Sons Pvt. Ltd.) is building India's first AI-enabled state-of-the-art Semiconductor Foundry. This facility will produce chips for applications such as power management IC, display drivers, microcontrollers (MCU) and high-performance computing logic, addressing the growing demand in markets such as automotive, computing and data storage, wireless communications and artificial intelligence.

Tata Electronics is a subsidiary of the Tata Group. The Tata Group operates in more than 100 countries across six continents, with the mission "To improve the quality of life of the communities we serve globally, through long term stakeholder value creation based on leadership with Trust."

Job Description

We are seeking an experienced Process Integration Development (PID) Engineer – Embedded Source/Drain (eS/D) Epitaxy Integration for advanced CMOS technologies at 28nm and below, including FinFET nodes. This role is responsible for driving advanced CMOS Process Integration Development, with primary ownership of embedded Source/Drain (eS/D) epitaxy process integration, enabling technology development, device performance optimization, yield enhancement, and manufacturing readiness.

The successful candidate will drive embedded Source/Drain epitaxy process integration while working across FEOL integration, process-device interactions, silicon characterization, DOE development, process optimization, technology qualification, technology transfer, and high-volume manufacturing ramp. The role requires close collaboration with Process Module, Device, Yield, Reliability, Product Engineering, and Manufacturing teams.

At Tata Electronics Private Limited (TEPL), the Technology Development organization is responsible for developing, qualifying, and transferring various technology platforms from R&D into high-volume manufacturing, enabling world-class semiconductor technologies and manufacturing excellence.

Responsibilities

• Own embedded Source/Drain (eS/D) epitaxy process integration for advanced CMOS technologies (28nm and below), including selective epitaxial growth of SiGe, SiC, and SiP stressors, strain/stress engineering, dopant and junction optimization, eS/D integration scheme development, and thermal budget management to achieve target device performance, manufacturability, and reliability.
• Develop and optimize CMOS Process Integration technologies for 28nm and below technology nodes by driving process-device interactions, DOE-driven silicon learning, process characterization, and process window optimization.
• Analyze process integration trade-offs using strong semiconductor device physics to optimize transistor characteristics, including Vt, Id, Ioff, DIBL, SS, mobility, matching, variability, and reliability, while achieving target device performance and manufacturability.
• Support technology qualification, technology transfer, manufacturing readiness, and production ramp activities, enabling successful transition from R&D into high-volume manufacturing.
• Drive manufacturing excellence through defect reduction, process capability enhancement, process robustness, and yield ramp activities using SPC, Cp/Cpk analysis, defect Pareto analysis, excursion investigations, and root-cause analysis to improve process stability, device performance, and yield.
• Establish process-to-device and yield correlations through analysis of inline metrology, WAT/PCM, electrical characterization, defectivity, physical analysis, reliability, and yield data to identify integration risks, process sensitivities, and process optimization opportunities.
• Utilize DOE, TCAD, JMP, Python, statistical analysis, and advanced data analytics (AI/ML methodologies) to accelerate technology learning, process optimization, and yield enhancement. Experience with one or more of these tools is a plus.
• Collaborate with Device, Process Module, Yield, Reliability, Product Engineering, and Manufacturing teams to drive device characterization, reliability qualification, yield improvement, technology transfer, and production ramp.
• Provide technical expertise to solve complex process integration challenges while driving innovation, continuous improvement, and manufacturing excellence.

Essential Attributes

• Strong expertise in advanced CMOS Process Integration for 28nm and below technology nodes, with solid understanding of FEOL integration, process-device interactions, and semiconductor manufacturing.
• Demonstrated expertise in embedded Source/Drain (eS/D) epitaxy process integration, including selective epitaxial growth of SiGe, SiC, and SiP stressors, strain/stress engineering, dopant engineering, junction optimization, eS/D integration scheme development, and thermal budget management.
• Hands-on experience in 28nm planar CMOS or more advanced logic technology nodes. Experience with FinFET technology, advanced patterning, selective epitaxial growth, and next-generation device architectures is a plus.
• Strong semiconductor device physics foundation with the ability to optimize transistor performance parameters such as Vt, Id, Ioff, DIBL, SS, mobility, variability, matching, reliability, and manufacturability through process integration.
• Strong analytical and problem-solving skills with proven experience in DOE development, process characterization, statistical analysis, process window optimization, silicon learning, and root-cause analysis of process, device, yield, and reliability issues.
• Proven experience in technology qualification, technology transfer, manufacturing readiness, and production ramp, enabling successful transition from R&D into high-volume manufacturing.
• Demonstrated track record in yield improvement, defect reduction, SPC, Cp/Cpk enhancement, excursion management, process robustness, and high-volume manufacturing support for advanced semiconductor technologies.
• Ability to correlate inline metrology, WAT/PCM, electrical characterization, defectivity, physical analysis, reliability, and yield data to identify integration risks, process sensitivities, and process optimization opportunities.
• Experience with TCAD, JMP, Python, statistical tools, and advanced data analytics (AI/ML methodologies) is a plus.
• Strong cross-functional collaboration skills with Device, Process Module, Yield, Reliability, Product Engineering, and Manufacturing teams.
• Strong communication, technical presentation, and problem-solving skills, with the ability to drive innovation, continuous improvement, and technical decision-making in a fast-paced semiconductor technology development environment.

Qualifications

• M.S. or Ph.D. in Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or related field with 3+ to 10 years of experience.
• Bachelor’s degree in electrical engineering, Materials Science, Physics, Semiconductor Engineering, or related field with 7+ to 15 years of experience.
• Experience in 28nm planar CMOS, FinFET, or advanced logic technologies.
• Strong understanding of semiconductor device physics, process integration, DOE, statistical analysis, yield analysis, and process optimization.
• Excellent communication and cross-functional collaboration skills.