Lead ASIC DFT Engineer

Lead ASIC DFT Engineer

Contract | Remote

Job Descripti

onExperien

ce10+ years of hands-on experience in ASIC Design-for-Test (DF

T)
Role Summ

aryWe are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issu

es.The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yie

ld.
Responsibili

• tiesLead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC desi
• gns.Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testabil
• ity.Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up pha
• ses.Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon iss
• ues.Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analy
• sis.Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation iss
• ues.Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/de
• bug.Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integrat
• ion.Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test qual
• ity.Act as a technical escalation point for advanced DFT and post-silicon debug iss
• ues.Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automat
• ion.Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productiv

ity.Required Skills & Qualificat

• ionsStrong hands-on experience in ASIC DFT with end-to-end owners
• hip.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage conce
• pts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon de
• bug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA to
• ols.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analy
• sis.Experience with MBIST implementation and verification; SMS experience prefer
• red.Experience with scan architecture and scan chain stitching; Tessent/SSN experience prefer
• red.Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementat
• ion.Proven post-silicon debug and silicon bring-up experie