Job Overview
We are seeking a talented Analog Layout Engineer with 3- 5 years of experience in advanced semiconductor technologies (5nm and below).
The ideal candidate will have hands-on expertise in custom layout design, FinFET technology nodes, and EDA tools like Cadence Virtuoso and Calibre.
This is a fantastic opportunity to work on cutting-edge analog and mixed-signal circuit layouts as part of a high-performance team.
Key Responsibilities
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Execute full custom layout design for high-speed analog and mixed-signal blocks.
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Collaborate closely with circuit design teams to interpret and implement layout specifications.
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Perform layout verification, including DRC, LVS, and parasitic extraction using industry-standard tools.
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Ensure compliance with foundry design rules and layout best practices for 5nm and below FinFET technologies.
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Address issues related to electromigration, IR drop (EMIR), and layout-dependent effects (LDE).
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Optimize layouts for performance, area, and reliability across PVT corners.
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Support tape-out and post-layout verification activities.
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Participate in design reviews and proactively resolve layout-related issues.
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Maintain proper documentation of layout guidelines, checklists, and review Skills & Expertise :
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Proven experience in custom analog layout for high-speed and precision circuits (e.g., PLLs, ADCs, LDOs, SerDes, etc.
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Strong working knowledge of FinFET nodes (6nm, 5nm or below) with exposure to leading foundries.
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Proficient in layout tools like Cadence Virtuoso, Calibre, and parasitic extraction tools.
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Sound knowledge of DRC, LVS, and EMIR verification methodologies.
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Understanding of layout effects such as matching, shielding, symmetry, and noise isolation.
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Familiarity with EDA scripting (Skill, Tcl, Python) is a plus.
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Strong problem-solving skills and attention to detail.
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Good communication and collaboration abilities in a team-based Join Us?
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Work on cutting-edge layout challenges with the latest process technologies.
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Join a fast-growing semiconductor team working on impactful silicon designs.
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Competitive compensation and career development opportunities
(ref:hirist.tech)