Job Description:
Responsibilities:
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Participate in chip level DFT architecture definition.
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Implement DFT schemes, including scan, boundary scan, Mem BIST and Logic BIST.
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Verify all DFT logics and test patterns with simulation
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Test modes static timing analysis
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Participate in ATE bring-up and debug the DFT patterns on ATE.
Requirements/Qualifications:
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Good understanding of the General DFT methodology such as BIST, SCAN, JTAG, ATPG and SSN
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Be familiar with Mentor / Synopsys DFT flow and tools
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Experience in developing constraints for synthesis/STA
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Multi-mode, multi-corner STA experience in 16nm and lower technology nodes, Understanding Sign-Off Checks
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Experience in silicon debug, diagnosis and yield improvement
Education/Certifications
Preferred Degree: MS Preferred Major: Microelectronics or related discipline
R024093