Job Description:

The Central Engineering Team is responsible for standard cell development and custom design solutions that power cutting-edge AI compute cores and CPUs. We are seeking

a motivated and technically strong engineer to join our team.

Job Description:

 Layout design of digital high-performance blocks

 Timing closure of the blocks with best PPA (power/performance/area)

 Debug LVS/DRC/ERC errors with verification tool

 Analyze the trade-offs and performance implications of different cell architectures

 Collaborate with design and layout engineers to optimize layout for area and performance

 Work with CAD, packaging and foundry teams in resolving layout and/or verification issues

Ideal Candidate Will Have:

 Strong understanding of physical implementation.

 Experience working with advanced semiconductor technologies.

 Experience in implementing low power and high-performance cores

 Excellent communication and cross-functional collaboration skills.

 Ability to analyze complex trade-offs and make data-driven decisions.

 Master’s degree with 6+ years or PhD with 3+ years of hands-on experience with Place and route tools; PhD in Engineering is a plus

Join us in shaping the next generation of high-performance compute technologies.

Additional Job Description:

Compensation And Benefits

The annual base salary range for this position is $120,000 - $192,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.