Hardware ASIC Signal & Power Integrity Simulation Engineer

We are seeking a Signal and Power Integrity Engineer to design, develop, and verify ASIC packaging for high-performance platforms.

Responsibilities include creating design rules for ultra-high-speed signaling, analyzing substrate signal and power integrity, and collaborating with teams to optimize solutions across interposers, substrates, and PCBs.

The role involves developing detailed ASIC packages, conducting post-layout extraction, and resolving technical issues with vendors and system partners.

Qualifications include a Bachelor's, Master's, or PhD in Electrical Engineering with relevant experience in high-speed design, SI/PI simulations, layout review, and circuit analysis.

Preferred skills encompass experience with high-bandwidth memory, advanced packaging technologies, and communication of complex technical concepts.

This role requires living near the San Jose, CA office and commuting at least 4-5 days weekly.