Front End Engineer, SoC

Location: Ho Chi Minh city, Vietnam

Open to candidates with 6–12 months of experience (including internships).

Only Vietnamese citizens are eligible to apply

About Connexus:

Connexus is a fast-growing fabless semiconductor startup focused on AI chips and advanced chip design services. We aim to empower the next generation of AI workloads with cutting-edge technologies, while building a collaborative, innovative, and people-first culture.

Key Responsibilities:

• Develop and verify RTL blocks for SoC front-end design using Verilog / SystemVerilog
• Write simulation testbenches, run functional verification, and debug waveform results
• Use VCS and DVE for simulation, debug, and result analysis
• Support FPGA prototyping and design validation using Vivado
• Participate in micro-architecture discussions, design reviews, and technical problem-solving
• Learn and apply front-end design concepts such as clocking, reset, FSM, pipeline, and CDC basics
• Review synthesis, timing, and area results with guidance from senior engineers
• Work with both commercial and open-source front-end tools where appropriate
• Document design assumptions, implementation notes, and verification results
• Collaborate closely with senior RTL engineers on real project development and tape-out related activities

Requirements:

• Final-year student or recent graduate in E lectrical Engineering, Electronics Engineering, Computer Engineering , or a related field
•  Open to interns, trainees, fresh graduates, and candidates with up to 1 year of experience (including internships)
• Hands-on experience with Verilog or SystemVerilog through coursework, university labs, or personal projects
• Basic understanding of RTL design, simulation, waveform debugging, and testbench development
• Familiarity with front-end development tools such as:
• Vivado
• VCS / DVE
• Open-source tools such as Verilator, GTKWave, Icarus Verilog, or Yosys are a plus
• Basic understanding of timing concepts, clock domains, reset behavior, and pipelined design
• Able to read technical documentation and communicate clearly in an engineering environment
• Willingness to learn from hands-on work with real semiconductor development flows

Nice to have:

• Experience with FPGA lab projects or academic chip design projects
• Exposure to UVM , scripting ( Python, Tcl, Shell ), or lint/synthesis flows
• Interest in SoC architecture, AI accelerators, or ASIC front-end development

Why join Connexus:

• Direct access to senior engineers with experience at top-tier semiconductor companies.
• Work on production SoC projects
• Competitive salary and benefits are offered for full-time hires.
• Strong interns are considered for full-time roles at the end of the period of the internship.
• Allowance for internship: 2,000,000 VND/ month

Working address: 5th Floor, Hado South Building, 60 Truong Son Str., Tan Son Hoa Ward, Ho Chi Minh City, Vietnam

Apply via email: [email protected]