FPGA designer

A global defense technology leader specializing in the design, engineering, and manufacturing of advanced sonar systems and maritime acoustic technologies.

The enterprise develops high-reliability, mission-critical signal processing systems deployed by naval and security forces worldwide.

Operating at the cutting edge of underwater acoustics and defense-grade electronics, the company provides a highly stable, collaborative, and tight-knit working environment that blends bleeding-edge tech innovation with a family-oriented corporate culture.

The primary R&D facility is located in the Central region of Israel, offering long-term professional stability within an elite defense engineering hub.

Position Overview-

• Senior FPGA Design Engineer owning the entire silicon development lifecycle of next-generation hardware platforms, from initial architecture and characterization to full physical integration and production hand-off.
• Designing and modeling high-throughput, low-latency digital logic blocks tailored to process complex, real-time sonar acoustic streams and sensor arrays.
• Developing inside a highly dynamic, multi-disciplinary ecosystem, interfacing directly with high-frequency RF front-ends and multi-gigabit high-speed data paths.
• Partnering cross-functionally with Hardware Design, Logic Verification, Systems, and Embedded Software engineering squads to ensure seamless hardware-software integration.
• Core Domain & Ecosystem- FPGA Design, VHDL, Xilinx & Altera Silicon, Vivado Design Suite, ModelSim, High-Speed Interfaces, Communication Protocols (Ethernet, I2C, SPI, UART), MicroBlaze, Soft-Core Processors, and RF/Signal Processing Integration.

Requirements-

• Academic Background: B.Sc. in Electrical Engineering, Electronic Engineering, Computer Science, or an equivalent exact science discipline from a recognized academic institution – Mandatory
• 5+ years of proven, hands-on professional experience specializing in FPGA architecture, logic design, and implementation – Mandatory
• Advanced programming mastery in VHDL hardware description language – Mandatory
• Robust, practical experience utilizing Xilinx Vivado development workflows and design suites – Mandatory
• Direct technical experience implementing and validating high-speed communication interfaces and multi-gigabit protocols – Mandatory
• Thorough professional familiarity with standard hardware communication buses and interfaces, including Ethernet (ETH), I2C, UART, and SPI – Mandatory
• Practical engineering experience designing with soft-core processor architectures (such as MicroBlaze) embedded within logic fabrics – Mandatory
• Hands-on proficiency setting up testbenches and executing digital simulations using ModelSim or similar industry-standard simulation tools – Mandatory
• Comprehensive knowledge covering both Xilinx and Altera silicon portfolios – Mandatory