FPGA Engineer

Unilink Ltd. โ†—

๐Ÿ“ Holon, Israel ๐Ÿ‡ฎ๐Ÿ‡ฑ

full-time
mid-level
Posted โ€”

Key Skills

FPGAVHDLVerilogXilinxModelSim

Industry

SemiconductorConsumer Electronics

Job Description

ืžืฉืจืช ื“ืจื•ืฉ: ืžื”ื ื“ืก/ืช FPGA ื‘ื›ื™ืจ/ื”

ืื•ื“ื•ืช ื”ืชืคืงื™ื“

ืื ื• ืžื—ืคืฉื™ื ืžื”ื ื“ืก/ืช FPGA ืžื™ื•ืžืŸ/ืช ื•ื‘ืขืœ/ืช ืชืฉื•ืงื” ืœืชื—ื•ื, ืขื ื ื™ืกื™ื•ืŸ ืžืขืฉื™ ืžื•ื›ื— ืฉืœ 5 ืฉื ื™ื ืœืคื—ื•ืช,

ื‘ืชืคืงื™ื“ ื–ื” ืชื™ืงื—/ื™ ื—ืœืง ืžืจื›ื–ื™ ื‘ืชื›ื ื•ืŸ, ืคื™ืชื•ื—, ืกื™ืžื•ืœืฆื™ื” ื•ื”ื˜ืžืขื” ืฉืœ ืžืขืจื›ื•ืช ืœื•ื—ืžื” ืืœืงื˜ืจื•ื ื™ืช ืžื‘ื•ืกืกื•ืช FPGA, ื•ืชืชืจื•ื/ื™ ื™ืฉื™ืจื•ืช ืœืคื™ืชื•ื— ืคืชืจื•ื ื•ืช EW ืžื”ื“ื•ืจ ื”ื‘ื, ื”ืžืชืžื•ื“ื“ื™ื ืขื ื”ืื™ื•ืžื™ื ื”ืžื•ืจื›ื‘ื™ื ื•ื”ืžืฉืชื ื™ื ื‘ื™ื•ืชืจ ื‘ืฉื“ื” ื”ืงืจื‘ ื”ืžื•ื“ืจื ื™.

ื”ืขื‘ื•ื“ื” ื›ื•ืœืœืช ืฉื™ืชื•ืฃ ืคืขื•ืœื” ืฆืžื•ื“ ืขื ืฆื•ื•ืชื™ื ืจื‘-ืชื—ื•ืžื™ื™ื: ื—ื•ืžืจื”, ืชื•ื›ื ื”, ืื™ืžื•ืช ื•ื”ื ื“ืกืช ืžืขืจื›ืช, ืœืฆื•ืจืš ืืกืคืงืช ืคืชืจื•ื ื•ืช FPGA ื‘ืขืœื™ ื‘ื™ืฆื•ืขื™ื ื’ื‘ื•ื”ื™ื ื•ืžื•ื›ื•ื•ื ื™ ืžืฉื™ืžื” โ€“ ืžืฉืœื‘ ื”ืงื•ื ืกืคื˜ ื•ืขื“ ื™ื™ืฆื•ืจ ื•ื”ื˜ืžืขื”.

ื“ืจื™ืฉื•ืช ื—ื•ื‘ื”

  • ื”ืฉื›ืœื”: ืชื•ืืจ ืจืืฉื•ืŸ ื‘ื”ื ื“ืกืช ื—ืฉืžืœ, ื”ื ื“ืกืช ืžื—ืฉื‘ื™ื, ื”ื ื“ืกืช ืืœืงื˜ืจื•ื ื™ืงื” ืื• ืชื—ื•ื ื˜ื›ื ื™ ืจืœื•ื•ื ื˜ื™ ืื—ืจ.
  • ื ื™ืกื™ื•ืŸ: 5 ืฉื ื•ืช ื ื™ืกื™ื•ืŸ ืžืงืฆื•ืขื™ ื‘ืชื›ื ื•ืŸ ื•ืคื™ืชื•ื— FPGA.
  • ืฉืœื™ื˜ื” ื‘-HDL: ืฉืœื™ื˜ื” ื’ื‘ื•ื”ื” ื‘-VHDL ื•/ืื• Verilog ืœืชื›ื ื•ืŸ RTL.
  • ื›ืœื™ ืคื™ืชื•ื—: ื ื™ืกื™ื•ืŸ ืžื•ื›ื— ืœืคื—ื•ืช ื‘ืื—ืช ืžืกื‘ื™ื‘ื•ืช ื”ืคื™ืชื•ื— ืฉืœ ื™ืฆืจื ื™ FPGA:
  • Xilinx/AMD (Vivado, Vitis, ISE) ืื• Intel/Altera (Quartus Prime, Platform Designer/Qsys).
  • ืกื™ืžื•ืœืฆื™ื”: ื ื™ืกื™ื•ืŸ ื‘ื‘ื ื™ื™ืช testbenches ืžืกื•ื“ืจื™ื ื•ื”ื™ื›ืจื•ืช ืขื ื›ืœื™ ืกื™ืžื•ืœืฆื™ื” ื›ื’ื•ืŸ ModelSim ื•-Questa.
  • ื ื™ืชื•ื— ืชื–ืžื•ื ื™ื: ื”ื‘ื ื” ืžืขืžื™ืงื” ื‘-STA (ื ื™ืชื•ื— ืชื–ืžื•ื ื™ื ืกื˜ื˜ื™), ืื™ืœื•ืฆื™ ืชื–ืžื•ืŸ (SDC/XDC), ืžืขื‘ืจื™ ืฉืขื•ืŸ (CDC) ื•ื˜ื›ื ื™ืงื•ืช ืœืกื’ื™ืจืช ืชื–ืžื•ื ื™ื.
  • ื™ืกื•ื“ื•ืช ืชื›ื ื•ืŸ ื“ื™ื’ื™ื˜ืœื™: ื™ื“ืข ื—ื–ืง ื‘ืœื•ื’ื™ืงื” ื“ื™ื’ื™ื˜ืœื™ืช, ืชื›ื ื•ืŸ ืžื›ื•ื ื•ืช ืžืฆื‘ื™ื (FSM), pipelining, ืืจื›ื™ื˜ืงื˜ื•ืจื•ืช DSP ื•ืื•ืคื˜ื™ืžื™ื–ืฆื™ื” ืฉืœ ืžืฉืื‘ื™ FPGA.
  • ื“ื™ื‘ื•ื’: ื ื™ืกื™ื•ืŸ ื‘ื›ืœื™ ื“ื™ื‘ื•ื’ ืฉืœ FPGA (ILA/ChipScope, SignalTap) ื•ืฉื™ืžื•ืฉ ื‘ืฆื™ื•ื“ ืžืขื‘ื“ื”.
  • ืกืงืจื™ืคื˜ื™ื ื•ืื•ื˜ื•ืžืฆื™ื”: ื ื™ืกื™ื•ืŸ ื‘ืฉืคื•ืช ืกืงืจื™ืคื˜ื™ื ื›ื’ื•ืŸ Python, Tcl, Bash ืœืื•ื˜ื•ืžืฆื™ื” ืฉืœ ืชื”ืœื™ื›ื™ ืคื™ืชื•ื—, ื‘ื“ื™ืงื•ืช ื•ื‘ื ื™ื™ื”.
  • ื™ื›ื•ืœืช ื ื™ื”ื•ืœ ืžืฉื™ืžื•ืช ืžืจื•ื‘ื•ืช ื•ืขืžื™ื“ื” ื‘ืœื•ื—ื•ืช ื–ืžื ื™ื ื‘ืกื‘ื™ื‘ื” ื“ื™ื ืžื™ืช ื•ืžื”ื™ืจื”.
  • ืชืฉื•ืงื” ืœืœืžื™ื“ื” ืžืชืžื“ืช ื•ืœื”ื™ืฉืืจื•ืช ื‘ื—ื–ื™ืช ื˜ื›ื ื•ืœื•ื’ื™ื™ืช FPGA ื•ืคื™ืชื•ื— ืžื‘ื•ืกืก AI.