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Design Verification Engineer
Design Verification Engineer
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MediaTek
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Design Verification Engineer
MediaTek
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📍 Hsinchu, Taiwan 🇹🇼
full-time
junior
29000
Expired
Posted —
This job posting has expired
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Key Skills
verification
formal
Haskell
OCaml
documentation
Industry
Semiconductor
Telecommunications
Job Description
Job Description
Application of formal method in digital hardware or software verification
Literature survey and paper study of the state-of-the-art and industrial strength formal method
Conducting cross-team-wise technical training
Documentation writing and reviewing
The estimated salary is NT$29000-50000 per month, which is subject to candidates' qualification.
Requirement
Bachelor of Science degree in CS or Math major
Background in the logic, language and computation
Familiar with functional language (Haskell, Ocaml) and formal method
Goal-oriented and working independently with effective execution.
Good communication skills and good at English
Good at logic and critical thinking
1+ year working experience is a plus.
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Key Skills
verification
formal
Haskell
OCaml
documentation
Industry
Semiconductor
Telecommunications
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ASIC Digital Verification, Principal Engineer
@ Synopsys Inc, 📍Austin, TX
Staff Engineer, Digital IC Design
@ Marvell Technology, 📍Westborough
IC Design Verification Engineer
@ NXP Semiconductors, 📍Ottawa
SG ASIC/SoC Design Verification Engineer
@ TetraMem - Accelerate The World, 📍Singapore, Singapore
Senior Quantum Design Verification Engineer
@ Microsoft, 📍Redmond
Companies Hiring Design Verification Engineer
Micron Technology
1 opening · 📍Boise, Idaho
GlobalFoundries
2 openings · 📍Malta, NY
NXP Semiconductors
2 openings · 📍Eindhoven, Noord-Brabant
Synopsys Inc
2 openings · 📍Sunnyvale, California
TetraMem - Accelerate The World
2 openings · 📍San Jose, California
BAE Systems
1 opening · 📍London, UK
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