Design Verification Engineer

MediaTek 

📍 Hsinchu, Taiwan 🇹🇼

full-time
junior
29000
Expired
Posted —
This job posting has expired View All Design Verification Engineer Jobs

Key Skills

verificationformalHaskellOCamldocumentation

Industry

SemiconductorTelecommunications

Job Description

Job Description

  • Application of formal method in digital hardware or software verification
  • Literature survey and paper study of the state-of-the-art and industrial strength formal method
  • Conducting cross-team-wise technical training
  • Documentation writing and reviewing
  • The estimated salary is NT$29000-50000 per month, which is subject to candidates' qualification.

Requirement

  • Bachelor of Science degree in CS or Math major
  • Background in the logic, language and computation
  • Familiar with functional language (Haskell, Ocaml) and formal method
  • Goal-oriented and working independently with effective execution.
  • Good communication skills and good at English
  • Good at logic and critical thinking
  • 1+ year working experience is a plus.