Design Verification Engineer

Design Verification Engineer

• Write Functional and code coverage, digital design and verification of all areas of lifecycle

• Plan and debug tests

• Development of test cases, checkers, and scoreboards

• Develop a complete test bench in System Verilog with Universal Verification Methodology (UVM)

• Work on simulators like Verilog Compiler Simulator (VCS)

• Plan for Assertion, Coverage metrics and coverage closure to make sure designs are verified thoroughly

• Digital Design and Verification (ASIC & RTL)

• Work on modem processors and protocols like AHB, AXI and perform design verification on all areas of verification lifecycle

Tools:

• UVM Methodology, Verilog, System Verilog