Job Title: Design Verification Engineer (High Priority Requirement)

Location: San Francisco Bay Area

Employment Type: Contract

About the Role

We are looking for a motivated Design Verification Engineer to join our team on a high-priority requirement. The role involves developing test plans, creating verification environments, and ensuring functional correctness of hardware IPs and SoCs. This is an excellent opportunity for engineers with 5–8 years of hands-on experience to work on advanced verification projects and collaborate closely with design, architecture, and software teams.

Key Responsibilities

• Develop and execute test plans for block-level, IP-level, and SoC-level verification.
• Build and maintain UVM/SystemVerilog testbenches (drivers, monitors, agents, checkers, scoreboards).
• Write test cases and sequences (directed and random) to achieve coverage goals.
• Debug test failures and work with cross-functional teams to resolve issues.
• Track and drive both functional and code coverage closure.
• Contribute to documentation of methodology, verification results, and best practices.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 5–8 years of hands-on verification experience at block/IP/SoC level.
• Strong knowledge of SystemVerilog, UVM methodology, and RTL design basics.
• Proficiency with industry-standard simulation tools (VCS, Questa, Xcelium, etc.).
• Experience with ARM AMBA protocols (AXI, AHB, APB) and memory/cache subsystems.
• Familiarity with coverage-driven verification and writing assertions (SVA).

Preferred Skills

• Experience with ARM CHI or other coherency protocols.
• Exposure to formal verification tools (JasperGold, OneSpin).
• Understanding of emulation/prototyping platforms (Cadence Palladium, Mentor Veloce, Synopsys Zebu, FPGA).
• Scripting experience in Python, Perl, or TCL for automation and regression management.
• Knowledge of RAS features and QoS in interconnect fabrics.